EECE 320 Homework 2, Fall 2011

EECE 320 – Digital Systems Design Homework 2 Problem 2 [25 points]: The aim of this problem is to find a logic expression for the output F of the combinational logic circuit below as a function of the inputs (W, X, Y, and Z). (a) Derive the expression directly from the structure of the circuit without any simplification. Show steps of your derivation. (b) After deriving the logic expression from the given circuit, simplify it algebraically into a sum-of-products expression. (c) Rewrite the expression of F as a product of sums. (d) Write the truth table for the given circuit. (e) Using the truth table, write the canonical sum and canonical product. Problem 3 [25 points]: Solve Problem 4.14 Parts (c), (d), and (e), Problem 4.18 Part (e), and Problem 4.19 Part (b). Show steps of your work using corresponding Karnaugh maps. Problem 4 [20 points]: Solve Problems 4.35, and 4.36 from the textbook related to XOR and XNOR Gates. Problem 5 [30 points]: We want to design a circuit that performs multiplication of 2 numbers A and B each with 2 bits. The output of the circuit consists of the product P with 4 bits since the maximum number to handle is (11)x(11) = 3x3 = 9 = (1001). Design a minimal sum-of-products circuit. In your solution, write corresponding truth table as shown below and use Karnaugh maps for minimization. A1 A0 B1 B0 P3 P2 P1 P0 0 0 0 0 0 0 0 0 … … … … … … … … 1 1 1 1 1 0 0 1