EECE 320 Homework 3, Fall 2011

EECE 320 – Digital Systems Design Homework 3 Problem 1 [30 points] Write and test the Prime Number Detector architectures described in the following tables in the textbook: Tables 5-38, 5-40, and 5-45. Provide printouts of your code in addition to snapshots of the testing simulations waveforms. Problem 2 [40 points]: A 2-bit comparator circuit receives two 2-bit numbers, P=P1P0 and Q = Q1Q0. And produces an output G which is set to 1 only when P > Q. Design a minimal Product of Sum (POS) expression for this circuit. Write a VHDL entity and a data flow architecture that describes the circuit in terms of gates and write a test bench that tests all the possible 16 cases. Next, write a behavioral architecture for the circuit and test it with a test bench covering all 16 possibilities. Problem 3 [30 points] Write a VHDL entity and architecture for a combinational logic function with six input bits N5-N0 representing an integer between 0 and 63, and one output M7 that indicates whether the integer is a multiple of 7. Write a test bench that shows the results of simulations for the numbers: 6, 7, 10, 20, 21, 50, 63.