EECE 320 Homework 3 Solution, Summer 2011
American University of Beirut · Digital Systems Design · 9 pages · Prof. Ali Chehab · with solution
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EECE 320 HOMEWORK 3
Problem 1
Table 5-38
library ieee;
use ieee.std_logic_1164.all;
entity prime is
port (N: in std_logic_vector (3 downto 0);
F: out std_logic);
end prime;
architecture prime3_arch of prime is
signal N3L_N0, N3L_N2L_N1, N2L_N1_N0, N2_N1L_N0: STD_LOGIC;
begin
N3L_N0 <= '1' when N(3)='0' and N(0)='1' else '0';
N3L_N2L_N1 <= '1' when N(3)='0' and N(2)='0' and N(1)='1' else '0';
N2L_N1_N0 <= '1' when N(2)='0' and N(1)='1' and N(0)='1' else '0';
N2_N1L_N0 <= '1' when N(2)='1' and N(1)='0' and N(0)='1' else '0';
F<= N3L_N0 or N3L_N2L_N1 or N2L_N1_N0 or N2_N1L_N0;
end prime3_arch;
Table 5-40
library ieee;
use ieee.std_logic_1164.all;
entity prime is
port (N: in st_logic_vector (3 downto 0);
F: out std_logic);
end prime;
architecture prime4_arch of prime is
begin
with N select
F <= '1' when "0001",
'1' when "0010",
'1' when "0011" | "0101" | "0111",
'1' when "1011" | "1101",
'0' when others;
end prime4_arch;
Table 5-45 (function from table 5-25)
Page 1 of 9
library ieee;
use ieee.std_logic_1164.all;
entity prime is
port (N: in std_logic_vector (3 downto 0);
F: out std_logic);
end prime;
architecture prime7_arch of prime is
function CONV_INTEGER (X: STD_LOGIC_VECTOR) return INTEGER is
variable RESULT: INTEGER;
begin
RESULT := 0;
for i in X'range loop
RESULT := RESULT*2;
case X(i) is
when '0' | 'L' => null;
when '1' | 'H' => RESULT := RESULT+1;
when others => null;
end case;
end loop;
return RESULT;
end CONV_INTEGER;
begin
process(N)
variable NI: INTEGER;
begin
NI := CONV_INTEGER(N);
if NI=1 or NI=2 then F <= '1';
elsif NI=3 or NI=5 or NI=7 or NI=11 or NI=13 then F <= '1';
else F <= '0';
end if;
end process;
end prime7_arch;
Test Bench for the three tables:
Page 2 of 9
library ieee;
use ieee.std_logic_1164.all;
entity prime_tb is
end prime_tb;
architecture arch_tb of prime_tb is
component prime port (N: in std_logic_vector (3 downto 0);
F: out std_logic);
end component;
signal N: std_logic_vector (3 downto 0) := "0000";
signal F: std_logic;
begin
test: prime port map(N=>N, F=>F);
process
begin
N<="0000"; wait for 10 ns;
N<="0001"; wait for 10 ns;
N<="0010"; wait for 10 ns;
N<="0011"; wait for 10 ns;
N<="0100"; wait for 10 ns;
N<="0101"; wait for 10 ns;
N<="0110"; wait for 10 ns;
N<="0111"; wait for 10 ns;
N<="1000"; wait for 10 ns;
N<="1001"; wait for 10 ns;
N<="1010"; wait for 10 ns;
N<="1011"; wait for 10 ns;
N<="1100"; wait for 10 ns;
N<="1101"; wait for 10 ns;
N<="1110"; wait for 10 ns;
N<="1111";
wait;
end process;
end arch_tb;
Waveform for the three codes:
Page 3 of 9
The testing simulation waveform is the same for all three codes, the wave in yellow is the
output that detects prime numbers (=1 when X=1, 2, 3, 5, 7, 11, and 13):
Problem 2
Page 4 of 9
Q0
P0
P1
Q1
Circuit and expression:
The 2-bit comparator minimal sum-of-products circuit that produces a 1 output if P < Q is:
And its logic expression is: F = P1'.Q1 + P0'.Q1.Q0 + P1'. P0'.Q0
Entity and data flow architecture:
The VHDL entity and data flow architecture that describes the circuit in terms of gates are:
library ieee;
use ieee.std_logic_1164.all;
entity compare is
port(P: in std_logic_vector(1 downto 0);
Q: in std_logic_vector(1 downto 0);
F: out std_logic);
end compare;
architecture compare_arch of compare is
signal s1,s2,s3:std_logic;
begin
s1<= ((not P(1)) and Q(1)) ;
s2<= ((not P(0)) and Q(1) and Q(0));
s3<= ((not P(1)) and (not P(0)) and Q(0));
F<= s1 or s2 or s3;
end compare_arch;
Test Bench:
Page 5 of 9
library ieee;
use ieee.std_logic_1164.all;
entity compare_tb is
end compare_tb;
architecture arch_tb of compare_tb is
component compare port (P,Q: in std_logic_vector (1 downto 0);
F: out std_logic);
end component;
signal P,Q: std_logic_vector (1 downto 0);
signal F: std_logic;
begin
testBench : compare port map (P=>P, Q=>Q, F=>F);
process
begin
P<="00"; Q<="00"; wait for 10 ns;
Q<="01"; wait for 10 ns;
Q<="10"; wait for 10 ns;
Q<="11"; wait for 10 ns;
P<="01"; Q<="00"; wait for 10 ns;
Q<="01"; wait for 10 ns;
Q<="10"; wait for 10 ns;
Q<="11"; wait for 10 ns;
P<="10"; Q<="00"; wait for 10 ns;
Q<="01"; wait for 10 ns;
Q<="10"; wait for 10 ns;
Q<="11"; wait for 10 ns;
P<="11"; Q<="00"; wait for 10 ns;
Q<="01"; wait for 10 ns;
Q<="10"; wait for 10 ns;
Q<="11"; wait for 10 ns;
end process;
end arch_tb;
VHDL entity and behavioral architecture:
Page 6 of 9
library ieee;
use ieee.std_logic_1164.all;
entity compare is
port (P,Q: in std_logic_vector (1 downto 0);
F: out std_logic);
end compare;
architecture behav_arch of compare is
signal s1,s2,s3,s4: std_logic;
begin
process (P,Q)
begin
if ( (P="00" and Q= "01") or (P="00" and Q(1)='1')
or (P="01" and Q(1)= '1') or (P="10" and Q="11") ) then F<='1';
else F<= '0';
end if;
end process;
end behav_arch;
The test bench is the same as for the dataflow architecture.
Simulation waveform:
The testing simulation waveform is the same for both architectures, the output is equal to 1
when P < Q:
Problem 3
Page 7 of 9
VHDL entity and architecture:
library ieee;
use ieee.std_logic_1164.all;
entity multiple is
port (N: in std_logic_vector (5 downto 0);
M3: out std_logic;
M5: out std_logic);
end multiple;
architecture multiple_arch of multiple is
function CONV_INTEGER (X: STD_LOGIC_VECTOR) return INTEGER is
variable RESULT: INTEGER;
begin
RESULT := 0;
for i in X'range loop
RESULT := RESULT*2;
case X(i) is
when '0' | 'L' => null;
when '1' | 'H' => RESULT := RESULT+1;
when others => null;
end case;
end loop;
return RESULT;
end CONV_INTEGER;
begin
process(N)
variable temp: integer;
begin
temp := CONV_INTEGER(N);
if (temp rem 3)=0 then M3<='1';
else M3 <= '0';
end if;
if (temp rem 5)=0 then M5<='1';
else M5 <= '0';
end if;
end process;
end multiple_arch;
Test Bench:
Page 8 of 9
use ieee.std_logic_1164.all;
entity multiple_tb is
end multiple_tb;
architecture multiple_tb_arch of multiple_tb is
component multiple port (N: in std_logic_vector (5 downto 0);
M3: out std_logic;
M5: out std_logic);
end component;
signal N: std_logic_vector (5 downto 0);
signal M3,M5: std_logic;
begin
test: multiple port map (N,M3,M5);
process
begin
N<="000110"; wait for 10 ns; -- N=6
N<="001001"; wait for 10 ns; -- N=9
N<="001111"; wait for 10 ns; -- N=15
N<="010100"; wait for 10 ns; -- N=20
N<="010111"; wait for 10 ns; -- N=23
N<="101100"; wait for 10 ns; -- N=44
end process;
end multiple_tb_arch;
Simulation waveform:
The wave on top indicates whether the integer is a multiple of 3, and the one on the bottom
indicates whether it’s a multiple of 5.
Page 9 of 9