EECE 320 Homework 4 with Solution, Fall 2007
American University of Beirut · Digital Systems Design · 8 pages · with solution
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EECE 320 – Digital Systems Design
Homework 4
Fall 2007-2008
Problem 1 [20 points] Solve Problem 6.20 Parts (a), (c), and (e) in the textbook.
Problem 2 [20 points] Solve Problem 6.21 in the textbook.
Problem 3 [20 points]: Write VHDL code to implement an 8-to-3 priority encoder.
Provide printouts of your code including test bench file in addition to snapshots of the
obtained simulation waveforms.
Problem 4 [20 points] Solve Problem 6.55 in the textbook. The MSI devices to be used
are limited to 74x148 and 74x138.
Problem 5 [20 points] Solve Problem 6.57 in the textbook. Use VHDL and develop a
suitable test bench file. Provide printouts of your code including test bench file in addition
to snapshots of the obtained simulation waveforms.
EECE 320
Homework #4
VHDL
XXX
XXX
19/11/2007
American University of Beirut
Question 3
The code of my priority encoder is the following:
library IEEE;
use IEEE.std_logic_1164.all;
entity encoder8to3 is
port (
I: in STD_LOGIC_VECTOR (7 downto 0);
A: out STD_LOGIC_VECTOR (2 downto 0)
);
end encoder8to3;
architecture encoder8to3 of encoder8to3 is
function CONV_STD_LOGIC_VECTOR(arg: integer; size: integer)
return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
variable temp : integer;
begin
temp := arg;
for i in 0 to size-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
temp := temp/2;
end loop;
return result;
end;
begin
process (I)
variable j: integer;
begin
for j in 7 downto 0 loop
if I(j) = '1' then
A <= CONV_STD_LOGIC_VECTOR(j, 3);
exit;
end if;
end loop;
end process;
end encoder8to3;
The test bench to test this program is the following:
use IEEE.std_logic_1164.all;
entity combinational_tb is
end combinational_tb;
architecture combinational_tb_arch of combinational_tb is
component combinational port (
R_L: in std_logic_vector (7 downto 0);
A: out std_logic_vector (2 downto 0);
B: out std_logic_vector (2 downto 0);
AVALID: out std_logic;
BVALID: out std_logic;
ENA: in std_logic;
ENB: in std_logic);
end component;
signal R_L: std_logic_vector(7 downto 0):="11111111";
signal A: std_logic_vector(2 downto 0):="000";
signal B: std_logic_vector(2 downto 0):="000";
signal AVALID: std_logic;
signal BVALID: std_logic;
signal ENA: std_logic:='1';
signal ENB: std_logic:='1';
begin
UUT: combinational
port map (R_L=>R_L,A=>A,B=>B,AVALID=>AVALID,BVALID=>BVALID,
ENA=>ENA,ENB=>ENB);
process
begin
R_L <="11111110"; wait for 10 ns;
R_L <="11111101"; wait for 10 ns;
R_L <="11111011"; wait for 10 ns;
R_L <="11110111"; wait for 10 ns;
R_L <="11101111"; wait for 10 ns;
R_L <="11011111"; wait for 10 ns;
R_L <="10111111"; wait for 10 ns;
R_L <="01111111"; wait for 10 ns;
wait;
end process;
end combinational_tb_arch;
The waveform of the test bench:
Question 5
I was not really sure what the question wanted me to do with the B output so I made them
have the same characteristics as the A outputs.
This is the code for my circuit:
library IEEE;
use IEEE.std_logic_1164.all;
entity combinational is
port(
R_L: in std_logic_vector (7 downto 0);
A: out std_logic_vector (2 downto 0);
B: out std_logic_vector (2 downto 0);
AVALID: out std_logic;
BVALID: out std_logic;
ENA: in std_logic;
ENB: in std_logic);
end combinational;
architecture combinational_arch of combinational is
signal A_s: std_logic_vector(2 downto 0);
signal B_s: std_logic_vector(2 downto 0);
begin
with R_L select A_s <=
"000" when "11111110",
"001" when "11111101",
"010" when "11111011",
"011" when "11110111",
"100" when "11101111",
"101" when "11011111",
"110" when "10111111",
"111" when "01111111",
"000" when others;
A <= A_s when ENA='1' else "000";
with R_L select B_s <=
"000" when "11111110",
"001" when "11111101",
"010" when "11111011",
"011" when "11110111",
"100" when "11101111",
"101" when "11011111",
"110" when "10111111",
"111" when "01111111",
"000" when others;
B <= B_s when ENB='1' else "000";
process (A_s)
begin
if (A_s(0)='1' or A_s(1)='1' or A_s(2)='1')
then AVALID <= '1'; else AVALID <= '0';
end if;
end process;
process (B_s)
begin
if (B_s(0)='1' or B_s(1)='1' or B_s(2)='1')
then BVALID <= '1'; else BVALID <= '0';
end if;
end process;
end combinational_arch;
This is the test bench for this block:
library IEEE;
use IEEE.std_logic_1164.all;
entity combinational_tb is
end combinational_tb;
architecture combinational_tb_arch of combinational_tb is
component combinational port (
R_L: in std_logic_vector (7 downto 0);
A: out std_logic_vector (2 downto 0);
B: out std_logic_vector (2 downto 0);
AVALID: out std_logic;
BVALID: out std_logic;
ENA: in std_logic;
ENB: in std_logic);
end component;
signal R_L: std_logic_vector(7 downto 0):="11111111";
signal A: std_logic_vector(2 downto 0):="000";
signal B: std_logic_vector(2 downto 0):="000";
signal AVALID: std_logic;
signal BVALID: std_logic;
signal ENA: std_logic;
signal ENB: std_logic;
begin
UUT: combinational
port map (R_L=>R_L,A=>A,B=>B,AVALID=>AVALID,BVALID=>BVALID,
ENA=>ENA,ENB=>ENB);
process
begin
R_L <="11111111"; wait for 10 ns;
R_L <="11111110"; wait for 10 ns;
R_L <="11111101"; wait for 10 ns;
R_L <="11111011"; wait for 10 ns;
R_L <="11110111"; wait for 10 ns;
R_L <="11101111"; wait for 10 ns;
R_L <="11011111"; wait for 10 ns;
R_L <="10111111"; wait for 10 ns;
wait;
end process;
end combinational_tb_arch;
The waveform for this exercise looks like the following: