EECE 320 Homework 5 with Solution, Fall 2007
American University of Beirut · Digital Systems Design · 5 pages · with solution
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EECE 320
Homework 5
Fall 2007-2008
XXX
XXX
03/01/2008
EECE 320 – Digital Systems Design
Homework 4
Fall 2007-2008
Problem 1 [10 points] Solve Problem 7.7 in the textbook.
Problem 2 [15 points] Solve Problem 7.17 in the textbook.
Problem 3 [15 points] Solve Problem 7.19 in the textbook.
Problem 4 [15 points] Solve Problem 7.20 in the textbook.
Problem 5 [25 points] Write a new transition table and derive minimal-risk excitation and
output equations for the state table in Table 7-5 using the “one-hot” state assignment in
Table 7-6 and D flip-flops.
Compare the cost of your excitation and output logic (when realized with a two-level
AND-OR circuit) with the equations in the box on page 566. Compute the cost in terms of
the required gates.
Sketch the resulting logic diagram.
Make sure that your solution is neat and clear to be able to correct it.
Problem 6 [20 points]
(a) Draw a state diagram for the state machine described in Table 7-9.
(b) Write a VHDL program for the ones-counting state machine exactly as described by
the state table in Table 7-9. Develop a suitable test bench file to simulate your
program. Provide printouts of your code including test bench file in addition to
snapshots of the obtained simulation waveforms.
Question 6
b) The code for this question is:
library ieee;
use ieee.std_logic_1164.all;
entity counter is
port (CLOCK, x, y: in std_logic;
z: out std_logic);
end;
architecture counter_arch of counter is
type state_type is (s0,s1,s2,s3);
signal sreg,snext: state_type;
begin
process(CLOCK)
begin
if CLOCK'event and CLOCK='1' then
sreg<=snext;
end if;
end process;
process (x,y,sreg)
begin
case sreg is
when s0 =>
if x='0' and y='0' then snext<=s0;
elsif x=not y then snext<=s1;
else snext<=s2;
end if;
when s1 =>
if x='0' and y='0' then snext<=s1;
elsif x=not y then snext<=s2;
else snext<=s3;
end if;
when s2 =>
if x='0' and y='0' then snext<=s2;
elsif x=not y then snext<=s3;
else snext<=s0;
end if;
when s3 =>
if x='0' and y='0' then snext<=s3;
elsif x=not y then snext<=s0;
else snext<=s1;
end if;
when others => snext<=s0;
end case;
end process;
with sreg select
z<='1' when s0,
'0' when others;
end counter_arch;
The Test Bench for this question is the following:
library ieee;
use ieee.std_logic_1164.all;
entity counter_tb is
end;
architecture counter_tb_arch of counter_tb is
signal CLOCK,x, y, z: std_logic;
component counter
port (CLOCK, x, y: in std_logic;
z: out std_logic);
end component;
begin
UUT: counter port map (CLOCK=>CLOCK, x=>x, y=>y, z=>z);
process
begin
CLOCK<='1'; wait for 5 ns;
CLOCK<='0'; wait for 5 ns;
end process;
process
begin
x<='0'; y<='0'; wait for 10 ns;
x<='0'; y<='1'; wait for 20 ns;
x<='1'; y<='0'; wait for 15 ns;
x<='1'; y<='1'; wait for 10 ns;
x<='0'; y<='0'; wait for 10 ns;
x<='0'; y<='1'; wait for 20 ns;
x<='1'; y<='0'; wait for 15 ns;
x<='1'; y<='1'; wait for 10 ns;
x<='0'; y<='0'; wait for 10 ns;
x<='0'; y<='1'; wait for 20 ns;
x<='1'; y<='0'; wait for 15 ns;
x<='1'; y<='1'; wait for 10 ns;
x<='0'; y<='0'; wait for 10 ns;
x<='0'; y<='1'; wait for 20 ns;
x<='1'; y<='0'; wait for 15 ns;
x<='1'; y<='1'; wait for 10 ns;
wait;
end process;
end counter_tb_arch;
The wave form for this question is the following: