EECE 210 Problems 5.3.32, Fall 2010
American University of Beirut · Electric Circuits · 1 page
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K¥ OrCAD Capture CIS - Demo Edition - [/ - (SCHEMATIC1 : PAGE1)]
bl File Edit View Tools Place Macro PSpice Accessories Options Window Help
Deb ee Gs ef SASS
j SCHEMATICI-SS \a DOBABAK 4\@ ry @
wi
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cE i 2 3 : ‘ :
PSpice netlist generation complete
Creating PSpice Netlist
Writing PSpice Flat Netlist C:\UNZIPPED\P5_3_32[1]\P5.3.32\P5332-SCHEMATIC1.net
PSpice netlist generation complete
O items selected
a
al) Ol fs
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a ba
+ A
+ ¥
Bo
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Ix
a
ST
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=|
cadence -
BOQt@
v mA
= Place Part r
Part a @
Patt List: Y
DigClock Al
FileStim1 :
FileStim16
FileStim2
FileStim32
FileStim4
FileStim8
IAC v
Libraries:
ANALOG
Design Cache
EVALAA
SOURCE
TRANSISTOR
Packaging
Parts perPkg 1
Type: Homogeneous
(J Search for Part
Search For | SOURCE IE)
Path |C:\ORCAD\ORCAD_16.3_ DEMO\T |[_)
Libraries
~ —
X=5.80 Y=2.00
Select the lihrani te acid 14
Scale=100%