EECE 421 Exam 2, Fall 2010

PROF. AKKARY DEPT. OF ELECTRICAL AND COMPUTER ENGINEERING December 10, 2010 AMERICAN UNIVERSITY OF BEIRUT EECE 421 – COMPUTER Architecture Quiz 2 – Fall 2010 NAME: __________________________________________ ID: ___________________________ INSTRUCTIONS: (1) Page 1 of 5  THE DURATION OF THE EXAM IS TWO HOURS. NO TIME EXTENSION.  THE EXAM IS CLOSED-BOOK/CLOSED-NOTES.  USING CELL PHONES IS NOT ALLOWED IN THE EXAMINATION ROOM.  WRITE YOUR NAME AND ID. NUMBER IN THE SPACE PROVIDED ABOVE.  CIRCLE ONLY ONE ANSWER.  READ THE QUESTIONS CAREFULLY BEFORE ANSWERING.  IN SOME QUESTIONS, MORE THAN ONE CHOICE MAY BE A VALID ANSWER. CIRCLE THE BEST CHOICE YOU THINK IS THE MOST APPROPRIATE ANSWER TO THE QUESTION.  ALL QUESTIONS ARE EQUALLY WEIGHTED.  THERE IS NO PENALTY FOR WRONG ANSWERS.  USE THE BACK PAGES FOR SCRATCH IF NEEDED  CHECK THAT YOU HAVE A TOTAL OF 5 PAGES.  NO QUESTIONS ARE ALLOWED.  YOU CANNOT LEAVE THE EXAM ROOM FOR ANY REASON UNTIL YOU COMPLETE THE EXAM. (1) Which of the following statements about pipelining is FALSE: a. Out-of-order issue causes out-of-order completion. b. Write-after-read hazards do not occur in in-order issue pipelines. c. Write-after-write hazards can occur in in-order issue pipelines. d. Optimizing compilers make write-after-write and write-after read hazards more probable. e. Read-after-write hazards can be avoided with register renaming. (2) Which of the following statements is TRUE about the CDC computer that preformed dynamic scheduling with scoreboard: a. It used in-order issue and therefore did not encounter write-after-read hazards. b. It avoided write-after-read hazards by stalling some writes to the register file. c. It performed out-of-order completion and used reorder buffer to handle branch mispredictions. d. It avoided read-after-write hazards by stalling at the decode stage. e. It avoided write-after-write hazards by enforcing in-order completion using the scoreboard. (3) Which of the following statements is TRUE: a. The reorder buffer is a buffer for instruction results. b. Most microprocessors that feature out-of-order execution use a future file. c. A history buffer provides better performance than a reorder buffer. d. Instructions read operands or tags from the reorder buffer in program order. e. Instructions write results to the reorder buffer in-order. (4) Select the TRUE statement: A processor uses Tomasulo’s algorithm to execute the following code segment. The latency of each operation is also shown. Add R1, R2, R3 (2 cycles) Mul R1, R1, R4 (20 cycles) Ld R2, 0(R4) (3 cycles) Sub R2, R1, R5 (1 cycle) a. Issue order is Mul, Add, Ld, Sub b. Issue order is Add, Sub, Ld, Mul c. Issue order is Ld, Sub, Mul, Add d. Issue order is Mul, Ld, Sub, Add e. None of the above (5) Which of the following statements is TRUE: a. Tomqsulo’s algorithm avoids write-after-write hazards by register renaming. b. Tomasulo’s algorithm avoids write-after-write hazards by stalling at the decode stage. c. Tomasulo’s algorithm avoids write-after-write hazards by using a reorder buffer. d. Tomasulo’s algorithm avoids write-after-write hazards by writing results into the register file in-order. e. Tomasulo’s algorithm avoids write-after-write hazards using tag matching in the RF. (6) Which of the following statements is TRUE: a. Tomasulo’s algorithm avoids write-after-read hazards by writing results into the register file in-order b. Tomqsulo’s algorithm avoids write-after-read hazards using tag matching in the reservation stations. c. Tomasulo’s algorithm avoids write-after-read hazards by stalling at the decode stage. d. Tomasulo’s algorithm avoids write-after-read using tag matching in the register file. e. Tomasulo’s algorithm avoids write-after-read hazards by using a reorder buffer. Page 2 of 5 (7) Choose the one FALSE statement about addressing modes. a. Indirect branches get the upper 4 bits of the address from the PC. b. Base addressing adds an offset to a base address. c. Immediate addressing gets its operand from the instruction. d. PC relative addressing uses the lower 16 bit from the PC to compute the target. e. Indirect branches can jump to any address in memory. (8) Which of the following is TRUE? a. The most significant factor in computer performance is always the performance of its CPU. b. The length of out-of-order superscalar pipeline has no impact on performance. c. Adding processors to a computer system that uses multiple processors for separate tasks usually increases throughput. d. Benchmarks are programs specifically chosen to debug the dapapath and control of a microprocessor. e. The Millions of Instructions per Second (MIPS) is the only valid metric to measure performance of a computer. (9) Total CPU power is given by: P = ½ CV2freq. a. True b. False (10) The relative performance of two processors with the same instruction set architecture (ISA) can be judged by the number of cycles required to execute a program. a. True b. False (11) A web server CPU is busy with computation 40% of the time and waiting for I/O 60%. Speeding up the I/O by 2 times is better for overall performance than speeding up the CPU by 4 times. a. True b. False (12) Instruction Set Architectures differ in how they access register operands, but not memory operands. a. True b. False (13) Which of the following statements about pipelining is FALSE: a. Pipelining improves performance by increasing instruction throughput. b. Pipelining does not decrease the execution time of an individual instruction. c. The ideal CPI of a pipelined processor is at most one. d. The ideal speed-up of a k -stage pipelined processor over a single-cycle processor is 1/ k . e. Sophisticated addressing modes that update registers can complicate hazard detection. (14) Which of the following statements is TRUE: a. A delayed branch is a branch that is delayed due to control hazards. b. A delayed branch causes more instructions to be flushed after a branch misprediction. c. A delayed branch does not require support from a compiler. d. A delayed branch is a method to maintain correct control dependences. e. Delayed branches are less useful in superscalar processors than 1-wide processors. Page 3 of 5 (15) Which of the following statements is FALSE: a. Pentium Pro performed register renaming by assigning different registers in a register alias table to instructions that write the same destination register. b. Pentium Pro converted all CISC instructions to RISC-like micro-ops. c. Pentium Pro was 3-wide superscalar. d. Pentium Pro used one centralized set of reservation stations. e. Pentium Pro used a BTB for branch prediction. (16) A gshare predictor uses saturating counters state machines. The branch predictor state is 00 and the branch is predicted to be not taken. The next state will be: a. 00 b. 01 c. 10 d. 11 e. Need more information to determine the next state. (17) A local correlating branch predictor uses 10 history bits and 12 address bits. The size of the state machines array is: a. 512 entries b. 1K entries c. 2K entries d. 4K entries e. 2M entries (18) Choose the pair of terms that are related: a. History buffer, bimodal predictor b. History buffer, gshare predictor c. History buffer, combined branch predictor d. History buffer, out-of-order execution e. None of the above (19) The gshare and Bimodal arrays are non-tagged arrays. a. True b. False (20) A data cache miss always causes data hazard stalls. a. True b. False (21) A compiler can safely reorder the following instruction sequence. BEQ R1, R0, Label Div R4, R0, R5 a. True b. False (22) A Result Shift Register can be used to provide precise state in case of exceptions. a. True b. False Page 4 of 5 (23) VLIW consumes less power than superscalars because it uses less complex hardware, therefore less logic gates. a. True b. False (24) A Software pipelining does not help performance of superscalar and VLIW architectures. a. True b. False (25) A Software pipelining may not help performance of superscalar and VLIW architectures as much as loop unrolling. a. True b. False Page 5 of 5