EECE 421 Exam 3, Fall 2012

PROF. AKKARY DEPT. OF ELECTRICAL AND COMPUTER ENGINEERING AMERICAN UNIVERSITY OF BEIRUT EECE 421 – COMPUTER Architecture Quiz 3 – Fall 2012 NAME: __________________________________________ ID: ___________________________ INSTRUCTIONS: 1  THE DURATION OF THE EXAM IS 90 MINUTES. NO TIME EXTENSION.  THE EXAM IS CLOSED-BOOK/CLOSED-NOTES.  USING CELL PHONES IS NOT ALLOWED IN THE EXAMINATION ROOM.  WRITE YOUR NAME AND ID. NUMBER IN THE SPACE PROVIDED ABOVE.  CIRCLE ONLY ONE ANSWER.  READ THE QUESTIONS CAREFULLY BEFORE ANSWERING.  IN SOME QUESTIONS, MORE THAN ONE CHOICE MAY BE A VALID ANSWER. CIRCLE THE BEST CHOICE YOU THINK IS THE MOST APPROPRIATE ANSWER TO THE QUESTION.  ALL QUESTIONS ARE EQUALLY WEIGHTED.  THERE IS NO PENALTY FOR WRONG ANSWERS.  USE THE BACK PAGES FOR SCRATCH IF NEEDED  CHECK THAT YOU HAVE A TOTAL OF 5 PAGES.  NO QUESTIONS ARE ALLOWED.  YOU CANNOT LEAVE THE EXAM ROOM FOR ANY REASON UNTIL YOU COMPLETE THE EXAM. Consider the following loop that adds two single precision floating point arrays and the writes the result in both arrays. Assume 5 stage MIPS pipeline with complete bypass, 3 cycles floating point Add execution unit, and BEQ execution of the condition and target in the decode stage. Assume that the pipeline does not perform delayed branch execution, (i.e., BEQ jumps to target immediately without allowing the pipeline to execute the next instruction after the branch in program memory). Loop: Ld F0, 0(R1) Ld F1, 0(R2) Add F2, F0, F1 St F2, 0(R1) St F2, 0(R2) Add R1, R1, #4 Add R2, R2, #4 BNE R2, R4, Loop 1. Without unrolling or software scheduling, how many cycles per iteration it takes to execute the loop. Round up if the answer is a fraction: a. 7 cycles b. 8 cycles c. 9 cycles d. 10 cycles e. 11 cycles f. 12 cycles g. 13 cycles h. None of the above Loop: Ld F0, 0(R1) Ld F1, 0(R2) Stall Add F2, F0, F1 Stall Stall St F2, 0(R1) St F2, 0(R2) Add R1, R1, #4 Add R2, R2, #4 Stall BNE R2, R4, Loop Stall 2. If the compiler schedules the loop without loop unrolling, how many cycles per iteration it takes to execute the loop. Round up if the answer is a fraction: a. 7 cycles b. 8 cycles c. 9 cycles d. 10 cycles e. 11 cycles f. 12 cycles g. 13 cycles h. None of the above Loop: Ld F0, 0(R1) Ld F1, 0(R2) Add R1, R1, #4 Add F2, F0, F1 Add R2, R2, #4 Stall St F2, -4(R1) 2 St F2, -4(R2) BNE R2, R4, Loop Stall 3. If the compiler unrolls the loop twice (i.e. new loop iteration consists of two old loop iterations), how many cycles per iteration it takes to execute the loop. Round up if the answer is a fraction: a. 7 cycles b. 8 cycles c. 9 cycles d. 10 cycles e. 11 cycles f. 12 cycles g. 13 cycles h. None of the above Loop: Ld F0, 0(R1) Ld F1, 0(R2) Stall Add F2, F0, F1 Stall Stall St F2, 0(R1) St F2, 0(R2) Ld F0, 4(R1) Ld F1, 4(R2) Stall Add F2, F0, F1 Stall Stall St F2, 4(R1) St F2, 4(R2) Add R1, R1, #8 Add R2, R2, #8 Stall BNE R2, R4, Loop Stall 4. If the compiler unrolls the loop twice and then performs instruction scheduling, how many cycles per iteration it takes to execute the loop. Round up if the answer is a fraction: a. 7 cycles b. 8 cycles c. 9 cycles d. 10 cycles e. 11 cycles f. 12 cycles g. 13 cycles h. None of the above Loop: Ld F0, 0(R1) Ld F1, 0(R2) Ld F2, 4(R1) Add F4, F0, F1 Ld F3, 4(R2) Add R1, R1, #8 Add R2, R2, #8 Add F5, F2, F3 St F4, -8(R1) St F4, -8(R2) 3 St F5, -4(R1) St F5, -4(R2) BNE R2, R4, Loop Stall 5. The compiler unrolls the loop twice and schedules the instructions on a 2-wide superscalar with one floating point execution unit, and one load/store execution port. Complete the next statement: Cycles per iterations to execute the loop = 5.5 Loop: Ld F0, 0(R1) Add R1, R1, #8 Ld F1, 0(R2) Add R2, R2, #8 Ld F2, -4(R1) Ld F3, -4(R2) Add F4, F0, F1 Stall Add F5, F2, F3 St F4, -8(R1) St F4, -8(R2) St F5, -4(R1) St F5, -4(R2) BNE R2, R4, Loop Stall 6. The compiler unrolls the loop twice and schedule the instructions to execute on a 3-wide VLIW processor that can execute a memory op, a floating op or an integer/branch op in the same cycle. Complete the next statement: Number of NOPs in the compiled loop = 20 Loop: Ld F0, 0(R1) Add R1, R1, #8 NOP Ld F1, 0(R2) Add R2, R2, #8 NOP Ld F2, -4(R1) NOP NOP Ld F3, -4(R2) NOP Add F4, F0, F1 NOP NOP NOP NOP NOP Add F5, F2, F3 St F4, -8(R1) NOP NOP St F4, -8(R2) NOP NOP St F5, -4(R1) NOP NOP St F5, -4(R2) BNE R2, R4, Loop NOP NOP NOP NOP 7. Assume the VLIW processor in the problem above uses stop bits. Complete the next statement: Number of operations in the compiled loop = 13 8. An Itanium EPIC compiler uses data speculation to move the load instruction and the instructions that uses the load data in the following code above the store. Store R1, (R2) Ld R3, (R4) Add R5, R3, #1 Complete the next statement: The compiled code segment will have 7 instructions. 4 Scratch Page 5 Scratch Page 6