CSI 312 Exam 2, Fall 2011

Question #1: (25 points) Part (a) Show or list all of ei as the dependencies in this program. For each dependency, indicate which i instructions and register are involved. (5 points) Part (b) The pipelined datapath on the next page shows the fifth cycle of executing this program, including values for several of the stages. Fill in the ten remaining values, marked with a ? symbol, in the EX and MEM stages. (20 points; 2 points each) N.B.: * Assume that registers initially contain their number plus 200: $2 contains 202, $8 contains 208, etc. + Write your answers directly on the diagram, but write clearly. * Show decimal values, and write ‘X’ for any numbers that cannot be determined. 16 797 | 1D: add $2, $2, $3 : EX: sub $3, $8, $4 fora 500MHz (2ns clock One CPU man ufacturer has proposed the 10-stage pipeline abov pipeline: - machine. Here are the correspondences between this and the MIPS Instructions are fetched in the FET stage. = Register reading is performed in the REG stage. = ALU operations and memory accesses are both done i = Branches are resolved in the DET stage. s WRB is the writeback stage. n the EXE stage. Part (a) How much time is required to execute there are no dependencies or branches in the code? (5 points) one million instructions on this processor, Part (b) Without forwarding, how many stall cycles are needed for points) Iw $t0, 0($a0) add $v1, $t0, $tO Q stall cycles Part (c) tions would have to be flushed from the fa branch is miss-predicted, how many instruc ipeline? (5 points) {instruction should would hove +e be use Part (d) Assume that a program executes one million instructions. Of these, | which stall, and 10% of the instructions are branches. The CPU predicts branches correctly 75% of the time. How much time will it take to execute this program? (10 points) 5% are load instructions Memory Hierarchy / i Question #3: (15 points) Assume a processor has a byte addressabl 4 Bytes. If the student architect was to design.a direct-mapped cache of size 4 should the following be: e memory of 512 Kbytes and a cache block size of Kbytes, what a) The size of the memory address (4 points) 14 instar OS eget oy oe lyre Co b) How is the address partitioned for the cache design? Clearly show the fields and summarize the function of each field (4 points) A g™ ) = (10+2) UX in . \@ 4 o- 0 > ee oe Ww 4 9 WGK = \C | offset =@>= 2=M ¢) Which one of these fields is also stored in cache and why? (3 points) e= . validcte it she dato is correc | ord x mattheS e ——~ ”™ fa . jhe 2 d) What is the total size in bytes for each cache? (4 points) 1) oll padatier 27(mx3 (Aa—m-n -hi t 10 -\2) +1 = 1° (eax d+ Ga-1a) + ) Question # 4: (10 points) ge eee K 6 A cache currently has an average memory access time of 12 ns, a hit time of 8 ns, and a hit rate of 90%. If doubling the size of the cache increases the hit time by 25% and increases the hit rate to 96%, what will the new average memory access time (AMAT) be ? Roy Hewoy acces Kye af 12NS - hit we = ¥us es ; Lt rote = qos. ANAT hth Gwe X litrote + (mics robe x { = ANA = pigscake Kmisspancdeg, lark Lime x uttiate missrate « miss penalty a _ a PORT 2S | sone new AMAT = (1.28 AG, 0.46 ) st —19,535n9