EECE 320 Midterm, Fall 2008

American University of Beirut Faculty of Engineering and Architecture Electrical and Computer Engineering Department EECE 320 Digital Systems Design Midterm Friday, November 21st, 2008 Name ________________________ Dr. Lama Hamandi ID ________________________ Duration: 90 minutes. Question 1 15 Question 2 30 Question 3 10 Question 4 5 Question 5 10 Question 6 15 Question 7 15 Total Grade 100 Instructions:  Check to insure that you have a complete copy of the examination. There are 7 Questions, and a total of 11 pages (including two blank pages).  This examination is closed book and closed notes.  Only one question is allowed for each student during the exam.  The use of Electronic calculators or other equipment is not allowed during the examination.  No use of scratch paper is allowed. You should work your Questions directly on the Question statement sheet in the appropriate space only. You may use the backside of the exam sheets as appropriate.  It is recommended that you read the whole exam before attempting any one Question.  Include all steps and calculations as appropriate for maximum credit. Be clear, brief, and specific in your answers. Good Luck Question 1: (15 points) ---------------------------------------- proposed time 10 minutes What is the sum of hexadecimal 0F4A and FE26? _____________ Subtract in binary using the 2’s complement representation: 010001001 – 01001101 = _____________ Convert: 2345.7510 = ( )2 = ( )BCD = ( )16 Question 2: (30 points) ---------------------------------------- proposed time 20 minutes Design an iterative network for adding three positive binary numbers. The three numbers are designated as xn…x3x2x1x0, yn…y3y2y1y0, zn…z3z2z1z0. A typical cell for this adder is of the form: (Hint: Each cell should have two carry in from the previous stage, and two carry out to the next stage). 1. Design the typical cell using Full adders. (5 points) 2. Write the VHDL code to define the entity Typical_Cell, and write the most appropriate architectural description for this entity. (10 points) EECE320 Digital Systems Design – Midterm Fall 2008-2009 3 EECE320 Digital Systems Design – Midterm Fall 2008-2009 4 3. Draw the circuit for a 4 bit adder using as many Typical Cell as needed (i.e. x, y and z are each a 4 bit numbers). (5 points) 4. Write efficient VHDL code to define the entity 4-bit adder (of part 3), and write the structural architectural description for this entity. (10 points) EECE320 Digital Systems Design – Midterm Fall 2008-2009 5 EECE320 Digital Systems Design – Midterm Fall 2008-2009 6 Question 3: (10 points) ---------------------------------------------- proposed time 5 minutes Draw a circuit Diagram to realize the following function using only one AND gate and one OR gate: (A + B + C + D)(A+ B + C + E)(A + B + C + F) EECE320 Digital Systems Design – Midterm Fall 2008-2009 7 Question 4: (5 points) ---------------------------------------- proposed time 5 minutes Give a minimum product of sum form for the boolean function F(x,y,z) = ∑ m(1,3,6,7). EECE320 Digital Systems Design – Midterm Fall 2008-2009 8 Question 5: (10 points) ---------------------------------------- proposed time 10 minutes Factor F = X'Y'Z' + XYZ to a product of three terms. EECE320 Digital Systems Design – Midterm Fall 2008-2009 9 Question 6: (15 points) ---------------------------------------- proposed time 10 minutes Design a 5-to-32 decoder with active low enable using the minimum number of 74x138 decoders along with one AND gate and one OR gate only. Show all connections. EECE320 Digital Systems Design – Midterm Fall 2008-2009 10 Question 7: (15 points) ---------------------------------------- proposed time 10 minutes We would like to analyze the above circuit. a- Derive the truth table of F(W,X,Y,Z) and G(W,X,Y,Z) b- Write F and G as minimum expressions. EECE320 Digital Systems Design – Midterm Fall 2008-2009 11 MSB MSB