EECE 321 Syllabus, Spring 2012

American University of Beirut Faculty of Engineering and Architecture Department of Electrical and Computer Engineering EECE 321 Computer Organization Course Syllabus – Spring 2012 Instructor Information Instructor: Dr. Lama Hamandi Office: Bechtel, Room 406D Office Hours: M, F 11:30am -1:30pm, T 8:00am - 10:00am (by appointment) Extension: 3617 E-Mail: lh13@aub.edu.lb Catalog Description This course covers the organization of modern computer systems. In addition to learning how to program computers at the assembly level, students learn how to design the main components of a von Neumann computer system, including its instruction set architecture, datapath, control unit, memory system, input/output interfaces, and system buses. To consolidate the material presented in class, students work on assembly-language programming and datapath design assignments and a major computer interfacing project. Prerequisites  By Course o EECE 230 Computers and Programming. o EECE 320 Digital Systems Design.  By Topic o Computer programming using a high-level language. o Digital hardware design using hardware description languages (HDLs). Textbook  David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Revised Fourth Edition, Morgan Kaufmann Publishers. References 1  P. Ashenden, The Student’s Guide to VHDL, MKP Publishers, 2nd Edition, 2008.  D. Perry, VHDL: Programming by Example, McGraw Hill Publishers, 4th Edition, 2002.  J. Bhasker, A VHDL Primer, Third Edition, Prentice-Hall, 1999. Course Objectives At the end of the course, students should be able to: 1. Identify the hardware components of a computer system. 2. Explain how machine instructions and the data they operate on are represented, stored, and executed. 3. Explain the roles of the operating system, compiler, assembler, loader, and linker. 4. Identify key milestones in the evolution of computer systems. 5. Identify the basic components of an instruction-set architecture. 6. Explain the differences between machine programming models. 7. Explain how basic arithmetic, logic, memory, and control operations work. 8. Write simple programs in MIPS R2000 assembly language. 9. Explain how subroutines are commonly linked. 10. Explain why interrupts and exceptions occur and how they are handled. 11. Represent real numbers in fixed-point notation. 12. Explain how fixed-point notations affect the dynamic range of numerical values and the precision of arithmetic operations. 13. Represent real numbers in the single- and double-precision formats of the IEEE-754 floating-point notation. 14. Demonstrate how basic floating-point arithmetic operations are performed. 15. Explain the operation of fixed-point and floating-point arithmetic circuits. 16. Identify the factors affecting execution performance. 17. Identify the steps needed to fetch and execute the machine instructions of a given instruction set architecture. 18. Identify the datapath elements needed to implement a specific instruction set. 19. Explain the principles of hardwired and microprogrammed control. 20. Design the control units for single-cycle and multi-cycle implementations of a given instruction set. 21. Explain how datapath elements and control units are implemented in hardware. 22. Measure the impact of various architectural implementation strategies on performance. 23. Explain how exceptions are handled in the control unit. 24. Explain the principle of pipelining. 25. Explain the interdependencies between instruction set design and pipelining. 26. Identify the different types of pipeline hazards. 27. Describe how different pipeline hazards affect performance. 2 28. Describe different techniques for dealing with pipeline hazards. 29. Measure the impact of pipelining and pipeline hazards on performance. 30. Design the datapath and control unit of a pipelined implementation of a given instruction set. 31. Describe the effect of an exception on a pipelined datapath. 32. Identify the main components of the memory hierarchy. 33. Explain the differences between key semiconductor memory technologies. 34. Explain the organization of a DRAM chip. 35. Design and expand a simple memory system. 36. Explain how cache memories increase the apparent speed of memory. 37. Explain how virtual memory increases the apparent size of memory and supports the enforcement of memory protection mechanisms. 38. Explain how different secondary storage devices function. 39. Explain the differences between program-driven, interrupt-driven, and direct memory access (DMA) input/output mechanisms. 40. Identify the components of serial and parallel input/output interface circuits. 41. Design simple input/output interface circuits. 42. Explain the operation of common peripheral communication protocols and controllers, like RS-232C, FireWire, USB 2.0, Centronix, Ethernet, Bluetooth, infrared, and WiFi. 43. Explain how different devices coordinate the use of a bus. 44. Explain how information is transferred over synchronous and asynchronous buses. 45. Explain the operation of common bus protocols like PCI, and SCSI. Assessment  Attendance/attitude 5%  Assignments/Project 20%  Quiz 1 20%  Quiz 2 20%  Final Exam 35% 3 Topical Outline and Suggested Coverage Schedule No. Subjects covered 50 min. lectures 1 Computer Abstractions and Technology: Classes of computing applications and their characteristics, Applications and system software layers, Transforming high level programs to the language of hardware, Five components of a computer, Defining performance, CPU performance equation, Evolution of computer technology from vacuum tubes to ultra large scale integrated circuits, Integrated circuits manufacturing process, Power wall, its causes and impact on microprocessor architecture. 3 2 Language of the Computer: MIPS Instruction Set Architecture, Arithmetic, logic, memory and conditional operations, register, memory and immediate operands, MIPS instruction encoding formats, Signed and unsigned integer numbers, Memory addressing, Branch target addressing methods, Compiling loops, conditional statements, leaf functions, nested functions and recursive functions from C to MIPs, Caller-callee register saving and restoring MIPS convention, MIPS exception handling, Allocating space for new data on the stack, MIPs register conventions, MIPS memory allocation for program and data (text, stack, heap, static), strings and character representation, Steps for translating and starting a program: compiler, assembler, linker, loader, dynamically linked libraries, Brief introduction to X86 instruction set architecture. 8 3 Arithmetic for Computers: Review of integer add, multiply, and divide hardware, Using integer arithmetic hardware for fixed-point real numbers arithmetic, Single and double precision IEEE 754 standard floating-point formats, converting from decimal real numbers to single and double precision floating point binary numbers, floating-point add and multiply algorithms and hardware, Denormals and NANs, MIPS floating point registers, arithmetic operations and conditional operations. Comparing fixed-point and floating-point real number representations in term of dynamic range, performance, cost and precision. 6 4 The Processor: Overview of datapath and control for a basic MIPS processor, building a single cycle MIPS datapath and control, Overview of pipelining, Pipelined datapath and control, Data, structural and control hazards, Forwarding vs. stalling, Handling interrupts and exceptions. 8 5 Memory Hierarchy: The basics of caches, Direct-map, set-associative and fully- associative caches, Handling cache misses, Handling writes, Cache and memory hierarchy, Basic methods for improving cache performance, Virtual memory, Translating virtual to physical addresses, Page tables and page table registers, page faults, Translation Lookaside Buffer (TLB), Implementing protection with virtual memory. 8 6 Storage I/O and Interfacing: Diversity and characteristics of I/O devices, Disk and flash storage, Connecting processors memory and I/O devices, Connection basics, synchronous, asynchronous interconnects, The I/O interconnects of X86 processors: memory controller hub (north bridge) and I/O controller hub (south bridge), Interfacing I/O devices to the processor, memory and operating system, Sending commands to I/O devices, Memory mapped I/O, Communicating with the processor using polling and interrupts, Transferring data between a device and memory, Direct Memory Access transfers (DMA), DMA and the memory system. 8 4 Exam Schedule  Quiz 1: Saturday, March 31st, 2012 at 10:00 am in Wing D.  Quiz 2: Saturday, May 12th, 2012 at 10:00 am in Wing D.  Final Exam: TBD by the Registrar’s Office. Course Policies 1. All lectures begin on the hour. Late students may be refused entry to the classroom. 2. Attendance of all lectures is required. Students who miss a lecture are responsible for its contents. 3. The course withdrawal deadline is Friday, April 27, 2012. Students who accumulate 6 or more absences by Thursday, April 26, 2012 will be withdrawn from the course and will receive a grade of "W". Beyond this date, students who accumulate eight or more absences (excused or not) will receive a 10-point deduction on their final (course) grade. 4. Assignments and project deliverables must be submitted by the assignment deadline. Late assignments will be penalized (deduction of 20% per day). 5. Cheating in any of its forms, including plagiarism, will not be tolerated. Students who cheat or help other students to cheat will receive a grade of zero on the assignment, project, or exam in question. Students also may be subject to further disciplinary action as deemed necessary. 6. No makeup exam will be offered for missed quizzes. 5