CSI 212 Chapter 2 Slides, Spring 2012

Assembly Language for Intel-Based Assembly Language for Intel-Based Computers, 5 Computers, 5th th Edition Edition Chapter 2: IA-32 Processor Architecture (c) Pearson Education, 2006-2007. All rights reserved. You may modify and copy this slide show for your personal use, or for use in the classroom, as long as this copyright statement, the author's name, and the title are not changed. Slides prepared by the author Revision date: June 4, 2006 Kip Irvine Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 2 Chapter Overview Chapter Overview • General Concepts • IA-32 Processor Architecture • IA-32 Memory Management • Components of an IA-32 Microcomputer • Input-Output System Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 3 General Concepts General Concepts • Basic microcomputer design • Instruction execution cycle • Reading from memory • How programs run Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 4 Basic Microcomputer Design Basic Microcomputer Design • clock synchronizes CPU operations • control unit (CU) coordinates sequence of execution steps • ALU performs arithmetic and bitwise processing Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 5 Clock Clock • synchronizes all CPU and BUS operations • machine (clock) cycle measures time of a single operation • clock is used to trigger events one cycle 1 0 Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 6 What's Next What's Next • General Concepts • IA-32 Processor Architecture • IA-32 Memory Management • Components of an IA-32 Microcomputer • Input-Output System Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 7 Instruction Execution Cycle Instruction Execution Cycle • Fetch • Decode • Fetch operands • Execute • Store output Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 8 Multi-Stage Pipeline Multi-Stage Pipeline • Pipelining makes it possible for processor to execute instructions in parallel • Instruction execution divided into discrete stages Example of a non- pipelined processor. Many wasted cycles. Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 9 Pipelined Execution Pipelined Execution • More efficient use of cycles, greater throughput of instructions: For k states and n instructions, the number of required cycles is: k + (n – 1) Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 10 Wasted Cycles (pipelined) Wasted Cycles (pipelined) • When one of the stages requires two or more clock cycles, clock cycles are again wasted. For k states and n instructions, the number of required cycles is: k + (2n – 1) Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 14 How a Program Runs How a Program Runs Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 15 Multitasking Multitasking • OS can run multiple programs at the same time. • Multiple threads of execution within the same program. • Scheduler utility assigns a given amount of CPU time to each running program. • Rapid switching of tasks • gives illusion that all programs are running at once • the processor must support task switching. Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 16 IA-32 Processor Architecture IA-32 Processor Architecture • Modes of operation • Basic execution environment • Floating-point unit • Intel Microprocessor history Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 18 Basic Execution Environment Basic Execution Environment • Addressable memory • General-purpose registers • Index and base registers • Specialized register uses • Status flags • Floating-point, MMX, XMM registers Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 19 Addressable Memory Addressable Memory • Protected mode (Windows) • 4 GB • 32-bit address • Real-address and Virtual-8086 modes (DOS) • 1 MB space • 20-bit address Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 20 General-Purpose Registers General-Purpose Registers CS SS DS ES EIP EFLAGS 16-bit Segment Registers EAX EBX ECX EDX 32-bit General-Purpose Registers FS GS EBP ESP ESI EDI Named storage locations inside the CPU, optimized for speed. Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 21 Accessing Parts of Registers Accessing Parts of Registers • Use 8-bit name, 16-bit name, or 32-bit name • Applies to EAX, EBX, ECX, and EDX Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 22 Index and Base Registers Index and Base Registers • Some registers have only a 16-bit name for their lower half: Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 23 Some Specialized Register Uses Some Specialized Register Uses (1 of 2) (1 of 2) • General-Purpose • EAX – accumulator • ECX – loop counter • ESP – stack pointer • ESI, EDI – index registers • EBP – extended frame pointer (stack) • Segment • CS – code segment • DS – data segment • SS – stack segment • ES, FS, GS - additional segments Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 24 Some Specialized Register Uses Some Specialized Register Uses (2 of 2) (2 of 2) • EIP – instruction pointer • EFLAGS • status and control flags • each flag is a single binary bit Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 25 Status Flags Status Flags • Carry • unsigned arithmetic out of range • Overflow • signed arithmetic out of range • Sign • result is negative • Zero • result is zero • Auxiliary Carry • carry from bit 3 to bit 4 • Parity • sum of 1 bits is an even number Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 27 Intel Microprocessor History Intel Microprocessor History • Intel 8086, 80286 • IA-32 processor family • P6 processor family • CISC and RISC Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 28 Early Intel Microprocessors Early Intel Microprocessors • Intel 8080 • 64K addressable RAM • 8-bit registers • CP/M operating system • S-100 BUS architecture • 8-inch floppy disks! • Intel 8086/8088 • IBM-PC Used 8088 • 1 MB addressable RAM • 16-bit registers • 16-bit data bus (8-bit for 8088) • separate floating-point unit (8087) Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 29 The IBM-AT The IBM-AT • Intel 80286 • 16 MB addressable RAM • Protected memory • several times faster than 8086 • introduced IDE bus architecture • 80287 floating point unit Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 30 Intel IA-32 Family Intel IA-32 Family • Intel386 • 4 GB addressable RAM, 32-bit registers, paging (virtual memory) • Intel486 • instruction pipelining • Pentium • superscalar, 32-bit address bus, 64-bit internal data path Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 31 Intel P6 Family Intel P6 Family • Pentium Pro • advanced optimization techniques in microcode • Pentium II • MMX (multimedia) instruction set • Pentium III • SIMD (streaming extensions) instructions • Pentium 4 and Xeon • Intel NetBurst micro-architecture, tuned for multimedia Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 32 CISC and RISC CISC and RISC • CISC – complex instruction set • large instruction set • high-level operations • requires microcode interpreter • examples: Intel 80x86 family • RISC – reduced instruction set • simple, atomic instructions • small instruction set • directly executed by hardware • examples: • ARM (Advanced RISC Machines) • DEC Alpha (now Compaq) Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 33 What's Next What's Next • General Concepts • IA-32 Processor Architecture • IA-32 Memory Management • Components of an IA-32 Microcomputer • Input-Output System Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 34 IA-32 Memory Management IA-32 Memory Management • Real-address mode • Calculating linear addresses • Protected mode • Multi-segment model • Paging Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 35 Real-Address mode Real-Address mode • 1 MB RAM maximum addressable • Application programs can access any area of memory • Single tasking • Supported by MS-DOS operating system Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 36 Segmented Memory Segmented Memory Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset linear addresses one segment Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 37 Calculating Linear Addresses Calculating Linear Addresses • Given a segment address, multiply it by 16 (add a hexadecimal zero), and add it to the offset • Example: convert 08F1:0100 to a linear address Adjusted Segment value: 0 8 F 1 0 Add the offset: 0 1 0 0 Linear address: 0 9 0 1 0 Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 38 Your turn . . . Your turn . . . What linear address corresponds to the segment/offset address 028F:0030? 028F0 + 0030 = 02920 Always use hexadecimal notation for addresses. Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 39 Your turn . . . Your turn . . . What segment addresses correspond to the linear address 28F30h? Many different segment-offset addresses can produce the linear address 28F30h. For example: 28F0:0030, 28F3:0000, 28B0:0430, . . . Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 40 Protected Mode Protected Mode (1 of 2) (1 of 2) • 4 GB addressable RAM • (00000000 to FFFFFFFFh) • Each program assigned a memory partition which is protected from other programs • Designed for multitasking • Supported by Linux & MS-Windows Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 41 Protected mode Protected mode (2 of 2) (2 of 2) • Segment descriptor tables • Program structure • code, data, and stack areas • CS, DS, SS segment descriptors • global descriptor table (GDT) • MASM Programs use the Microsoft flat memory model Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 42 Flat Segment Model Flat Segment Model • Single global descriptor table (GDT). • All segments mapped to entire 32-bit address space Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 43 Multi-Segment Model Multi-Segment Model • Each program has a local descriptor table (LDT) • holds descriptor for each segment used by the program Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 44 Paging Paging • Supported directly by the CPU • Divides each segment into 4096-byte blocks called pages • Sum of all programs can be larger than physical memory • Part of running program is in memory, part is on disk • Virtual memory manager (VMM) – OS utility that manages the loading and unloading of pages • Page fault – issued by CPU when a page must be loaded from disk Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 45 What's Next What's Next • General Concepts • IA-32 Processor Architecture • IA-32 Memory Management • Components of an IA-32 Microcomputer • Input-Output System Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 46 Components of an IA-32 Microcomputer Components of an IA-32 Microcomputer • Motherboard • Video output • Memory • Input-output ports Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 47 Motherboard Motherboard • CPU socket • External cache memory slots • Main memory slots • BIOS chips • Sound synthesizer chip (optional) • Video controller chip (optional) • IDE, parallel, serial, USB, video, keyboard, joystick, network, and mouse connectors • PCI bus connectors (expansion cards) Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 48 Intel D850MD Motherboard Intel D850MD Motherboard dynamic RAM Pentium 4 socket Speaker IDE drive connectors mouse, keyboard, parallel, serial, and USB connectors AGP slot Battery Video Power connector memory controller hub Diskette connector PCI slots I/O Controller Firmware hub Audio chip Source: Intel® Desktop Board D850MD/D850MV Technical Product Specification Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 49 Video Output Video Output • Video controller • on motherboard, or on expansion card • AGP (accelerated graphics port technology)* • Video memory (VRAM) • Video CRT Display • uses raster scanning • horizontal retrace • vertical retrace • Direct digital LCD monitors • no raster scanning required * This link may change over time. Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 50 Sample Video Controller (ATI Corp.) Sample Video Controller (ATI Corp.) • 128-bit 3D graphics performance powered by RAGE™ 128 PRO • 3D graphics performance • Intelligent TV-Tuner with Digital VCR • TV-ON-DEMAND™ • Interactive Program Guide • Still image and MPEG-2 motion video capture • Video editing • Hardware DVD video playback • Video output to TV or VCR Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 51 Memory Memory • ROM • read-only memory • EPROM • erasable programmable read-only memory • Dynamic RAM (DRAM) • inexpensive; must be refreshed constantly • Static RAM (SRAM) • expensive; used for cache memory; no refresh required • Video RAM (VRAM) • dual ported; optimized for constant video refresh • CMOS RAM • complimentary metal-oxide semiconductor • system setup information • See: Intel platform memory (Intel technology brief: link address may change) Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 52 Input-Output Ports Input-Output Ports • USB (universal serial bus) • intelligent high-speed connection to devices • up to 12 megabits/second • USB hub connects multiple devices • enumeration: computer queries devices • supports hot connections • Parallel • short cable, high speed • common for printers • bidirectional, parallel data transfer • Intel 8255 controller chip Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 53 Input-Output Ports Input-Output Ports (cont) (cont) • Serial • RS-232 serial port • one bit at a time • uses long cables and modems • 16550 UART (universal asynchronous receiver transmitter) • programmable in assembly language Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 54 What's Next What's Next • General Concepts • IA-32 Processor Architecture • IA-32 Memory Management • Components of an IA-32 Microcomputer • Input-Output System Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 55 Levels of Input-Output Levels of Input-Output • Level 3: Call a library function (C++, Java) • easy to do; abstracted from hardware; details hidden • slowest performance • Level 2: Call an operating system function • specific to one OS; device-independent • medium performance • Level 1: Call a BIOS (basic input-output system) function • may produce different results on different systems • knowledge of hardware required • usually good performance • Level 0: Communicate directly with the hardware • May not be allowed by some operating systems Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 56 Displaying a String of Characters Displaying a String of Characters When a HLL program displays a string of characters, the following steps take place: Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 57 ASM Programming levels ASM Programming levels ASM programs can perform input-output at each of the following levels: Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 58 Summary Summary • Central Processing Unit (CPU) • Arithmetic Logic Unit (ALU) • Instruction execution cycle • Multitasking • Floating Point Unit (FPU) • Complex Instruction Set • Real mode and Protected mode • Motherboard components • Memory types • Input/Output and access levels Web site Examples Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. 59 42 69 6E 61 72 79 42 69 6E 61 72 79