CSI 312 Lecture 8, Fall 2011

Pipelining Facts  Multiple tasks operating simultaneously  Pipelining doesn’t help latency of single task, it helps throughput of entire workload  Pipeline rate limited by slowest pipeline stage  Potential speedup = Number of pipe stages  Unbalanced lengths of pipe stages reduces speedup  Time to “fill” pipeline and time to “drain” it reduces speedup A B C D 6 PM 7 8 9 T a s k O r d e r Time 30 40 40 40 40 20 The washer waits for the dryer for 10 minutes 9.2 Pipelining  Instruction execution is divided into k segments or stages  Instruction exits pipe stage k-1 and proceeds into pipe stage k  All pipe stages take the same amount of time; called one processor cycle  Length of the processor cycle is determined by the slowest pipe stage k segments Pipeline Performance  n:instructions  k: stages in pipeline  : clockcycle  Tk: total time 1)) ( (    n k Tk )1 ( 1     n k nk T T Speedup k n is equivalent to number of loads in the laundry example k is the stages (washing, drying and folding. Clock cycle is the slowest task time n k SPEEDUP  • Consider a k-segment pipeline operating on n data sets. (In the above example, k = 3 and n = 4.)  > It takes k clock cycles to fill the pipeline and get the first result from the output of the pipeline.  After that the remaining (n - 1) results will come out at each clock cycle.  > It therefore takes (k + n - 1) clock cycles to complete the task. SPEEDUP  If we execute the same task sequentially in a single processing unit, it takes (k * n) clock cycles.  • The speedup gained by using the pipeline is:  S = k * n / (k + n - 1 ) SPEEDUP  S = k * n / (k + n - 1 ) For n >> k (such as 1 million data sets on a 3- stage pipeline),  S ~ k  So we can gain the speedup which is equal to the number of functional units for a large data sets. This is because the multiple functional units can work in parallel except for the filling and cleaning- up cycles. Time taken between 1st and 4th instruction in nonpipelined design is 3 x 800 = 2400 ps Speed Up Equation for Pipelining pipelined d unpipeline Time Cycle CPI Pipeline stall CPI Cycle Time Ideal Ideal CPI Pipeline depth Speedup     pipelined d unpipeline Time Cycle Pipeline stall CPI Cycle Time 1 Pipeline depth Speedup    per Inst Stall cycles CPI pipelined Ideal CPI Average   For simple RISC pipeline, CPI = 1: Performance  Speed Up  Pipeline Depth; if ideal CPI is 1, then: 11 pipelined d unpipeline Time Cycle Pipeline stall CPI Cycle Time 1 Pipeline depth Speedup    CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle CPU time = Seconds = Instructions x Cycles x Seconds Program Program Instruction Cycle ° Time is measure of performance: latency or throughput ° CPI Law: