CSI 312 Lecture 9, Fall 2011

1 Data Hazards Revisited…  Data hazards occur when data is used before it is stored (Fig. 6.28) IM Reg IM Reg CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 Time (in clock cycles) sub $2, $1, $3 Program execution order (in instructions) and $12, $2, $5 IM Reg DM Reg IM DM Reg IM DM Reg CC 7 CC 8 CC 9 10 10 10 10 10/– 20 – 20 – 20 – 20 – 20 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Value of register $2: DM Reg Reg Reg Reg DM 2 Data Hazard Solution: Forwarding  Key idea: connect data internally before it's stored IM Reg IM Reg CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 Time (in clock cycles) sub $2, $1, $3 Program execution order (in instructions) and $12, $2, $5 IM Reg DM Reg IM DM Reg IM DM Reg CC 7 CC 8 CC 9 10 10 10 10 10/– 20 – 20 – 20 – 20 – 20 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Value of register $2 : DM Reg Reg Reg Reg X X X – 20 X X X X X Value of EX/MEM : X X X X – 20 X X X X Value of MEM/WB : DM (Fig. 6.29) 3 Data Hazard Solution: Forwarding  Add hardware to feed back ALU and MEM results to both ALU inputs (Fig. 6.32) PC Instruction memory Registers M u x M u x Control ALU EX M WB M WB WB ID/EX EX/MEM MEM/WB Data memory M u x Forwarding unit IF/ID Instruction M u x Rd EX/MEM.RegisterRd MEM/WB.RegisterRd Rt Rt Rs IF/ID.RegisterRd IF/ID.RegisterRt IF/ID.RegisterRt IF/ID.RegisterRs A B 4 Controlling Forwarding  Need to test when register numbers match in rs, rt, and rd fields stored in pipeline registers  "EX" hazard:  EX/MEM - test whether instruction writes register file and examine rd register  ID/EX - test whether instruction reads rs or rt register and matches rd register in EX/MEM  "MEM" hazard:  MEM/WB - test whether instruction writes register file and examine rd (rt) register  ID/EX - test whether instruction reads rs or rt register and matches rd (rt) register in EX/MEM Sub $2, $1, $3 And $12, $2, $5 Or $13, $6, $2 add $14, $2, $2 Sw $15, 100($2) 5 Forwarding Unit Detail - EX Hazard if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 6 Forwarding Unit Detail - MEM Hazard if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 7 EX Hazard Complication  What if a register is changed more than once?  add $1, $1, $2;  add $1, $1, $3;  add $1, $1, $4;  Answer: forward most recent result (in MEM stage) 8 Forwarding Unit Detail - MEM Hazard Revised if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (EX/MEM.RegisterRd ≠ ID/EX.RegisterRs) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (EX/MEM.RegisterRd ≠ ID/EX.RegisterRt) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 9 Fig (6.33) Forwarding Elaboration  Extra 2-1 mux needed for immediate instructions Added Mux 10 Data Hazards and Stalls  We still have to stall when register is loaded from memory and used in following instruction Reg IM Reg Reg IM CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 Time (in clock cycles) lw $2, 20($1) Program execution order (in instructions) and $4, $2, $5 IM Reg DM Reg IM DM Reg IM DM Reg CC 7 CC 8 CC 9 or $8, $2, $6 add $9, $4, $2 slt $1, $6, $7 DM Reg Reg Reg DM (Fig. 6.34) 11 Pipelined Processor with Hazard Detection PC Instruction memory Registers M u x M u x M u x Control ALU EX M WB M WB WB ID/EX EX/MEM MEM/WB Data memory M u x Hazard detection unit Forwarding unit 0 M u x IF/ID Instruction ID/EX.MemRead IF/IDWrite PCWrite ID/EX.RegisterRt IF/ID.RegisterRd IF/ID.RegisterRt IF/ID.RegisterRt IF/ID.RegisterRs Rt Rs Rd Rt EX/MEM.RegisterRd MEM/WB.RegisterRd (Fig. 6.36) A B 12 Hazard Detection Unit - Control Detail if (ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or ((ID/EX.RegisterRt = IF/ID.RegisterRt))) stall 13 Hazard detection unit - what happens  MUX zeros out control signals for instruction in ID  "squashes” the instruction  “no-op” propagates through following stages  IF/ID holds stalled instruction until next clock cycle  PC holds current value until next clock cycle (re- loads first instruction) Example - Pipelining 2 14