EECE 320 Final, Fall 2010

FACULTY OF ENGINEERING AND ARCHITECTURE AMERICAN UNIVERSITY OF BEIRUT FALL 2010 - 2011 FINAL EXAM DIGITAL SYTEMS DESIGN (EECE320) January 28, 2010 NAME: _____________________ ID: _____________________ Circle the name of your instructor: Ali Chehab Youssef Nasser CLOSED BOOK (2 HOURS) WRITE YOUR NAME AND ID NUMBER IN THE SPACE PROVIDED ABOVE. CALCULATORS ARE NOT ALLOWED. PROVIDE YOUR ANSWERS IN THE SPACE PROVIDED ON THE QUESTION SHEET. THE SCRATCH BOOKLET WILL NOT BE CONSIDERED IN GRADING. ______________________________________________________________________ Problem Total Points Earned Points 1 6 2 6 3 9 4 10 5 8 6 7 7 6 8 6 9 6 10 8 11 10 12 6 13 12 Total 100 EECE 320 FINAL EXAM 2/10 Problem 1 [6 points] Given F = A,B,C,D,E(0, 1, 4, 6, 8, 9, 11, 12, 14, 15, 18, 19, 21, 23, 29) A. Fill in the corresponding Karnaugh map A = 0 A = 1 B. Indicate the Essential Prime Implicants ___________________________________________________________ C. Indicate all other Prime Implicants ____________________________________________________________ Problem 2 [6 points] We would like to build a JK Flip-Flop using a T Flip-Flop with enable and combinational logic. Write down the expression of E and complete the following diagram to achieve this purpose. E = _______________________________ E Q QN T DE BC 00 01 11 10 00 01 11 10 DE BC 00 01 11 10 00 01 11 10 EECE 320 FINAL EXAM 3/10 Problem 3 [9 points] It is required to design a combinational network that converts from the (2421) code to the BCD code as given in the truth table below. Unused code words should be considered as don’t cares to simplify your design. Digit A B C D X Y Z 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 2 0 0 1 0 0 1 0 3 0 0 1 1 0 1 1 4 0 1 0 0 1 0 0 5 1 0 1 1 1 0 1 6 1 1 0 0 1 1 0 7 1 1 0 1 1 1 1 A. Plot the outputs of the network on the following Karnaugh maps. B. The expressions for X, Y and Z are: X = _________________________________________ Y = _________________________________________ Z = _________________________________________ EECE 320 FINAL EXAM 4/10 Problem 4 [10 points] 1. We would like to analyze the following clocked synchronous state machine. A. Write the next state equations for y1 and y2. y1* = ____________________________________ y2* = ____________________________________ B. Draw the transition/output table. w y2 y1 0 1 Z 0 0 0 1 1 1 1 0 y2* y1* C. Draw the state diagram EECE 320 FINAL EXAM 5/10 Problem 5 [20 points] Design a sequential circuit with 2 JK flip-flops A and B and 3 inputs E, F and G. If E=0 or F=0, the circuit remains in the same state regardless of G. When E=1, F=1 and G=0, the circuit goes through the transitions from 00 to 11, to 10, 01, back to 00, and repeats. When E=1, F=1 and G=0 the circuit goes through the transitions from 00 to 10, to 01, back to 00, and repeats. Fill the transition and excitation tables below when G=0 and then when G=1. G=0 EF AB 00 01 11 10 0 0 0 1 1 1 1 0 A*B* G=1 EF AB 00 01 11 10 0 0 0 1 1 1 1 0 A*B* Fill the Karnaugh maps below corresponding to JA, and KA and find their expressions. JA = _______________________________ KA = ________________________________ Problem 6 [7 points] A memory is usually specified by the number of words times the number of bits per word. If we have a memory of 256Kx16, how many address lines does the memory have: __________, how EF AB 00 01 11 10 0 0 0 1 1 1 1 0 JA*KA*JB*KB* EF AB 00 01 11 10 0 0 0 1 1 1 1 0 JA*KA*JB*KB* AB EF 00 01 11 10 00 01 11 10 AB EF 00 01 11 10 00 01 11 10 EECE 320 FINAL EXAM 6/10 many data lines does it have: ______________, and how many bits in total does it have (as a power of 2): ____________ A 128K x 32 RAM chip is designed in such a way that its cell array is square, i.e., it contains an equal number of bits per row and column. A row decoder is used to select a row, and a column decoder is used to select the appropriate word within a column. What is the number of address bits needed to acces a row: ______________ and what is the number of address bits needed to access 32 bits within a column: ________________ EECE 320 FINAL EXAM 7/10 Problem 7 [6 points] A 4-to-16 Decoder has 4 inputs A, B, C, D, and 16 outputs Y0, …, Y15. Design this decoder using 2-to-4 Decoders with Enable. Problem 8 [6 points] Design an 8-input multiplexer with data inputs D7, D6, …, D0 and control inputs S2, S1, and S0, using only 2-input multiplexers. EECE 320 FINAL EXAM 8/10 Problem 9 [6 points] We would like to implement the function given below using a 4-to-1 multiplexer as shown below. Indicate what should be connected to the inputs of the Multiplexer. A B C F 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 B C Problem 10 [8 points] For the following circuit, complete the corresponding timing diagram shown below. Assume all flip-flops are initialized to zero. X A B C I0 I1 Z I2 I3 S1 S0 CLK EECE 320 FINAL EXAM 9/10 Problem 11 [10 points] Using T flip-flops with Enable, design a counter that counts as follows: 0, 2, 4, 6, 8, 1, 3, 5, 9, 0, etc. In case of an illegal state like 10, 11, 12, 13, 14, and 15 we should use minimum risk and move the counter to the initial state of 0. A. Fill the next state table and excitation tables. A B C D A* B* C* D* E1 E2 E3 E4 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 B. Derive the excitation equations for E1, and E4. E1 E4 E1 = _____________________________ E4 = _____________________________ CD AB 00 01 11 10 00 01 11 10 CD AB 00 01 11 10 00 01 11 10 EECE 320 FINAL EXAM 10/10 Problem 12 [6 points] Using a Moore machine, design a sequence detector that would output a Z=1 only after detecting on its single input X, a sequence of 0011 or a sequence of 1100 and it stops at the final state, in other words, don’t check for X after the final state. A. Draw the state diagram in the space below. Problem 13 ( 12 points) Write a VHDL code to implement a Moore sequence detector that detects on a single input, X, two consecutive ones (11). EECE 320 FINAL EXAM 11/10