EECE 320 Final with Solution, Fall 2005

,_DEPARTMENT OF ELECTRICAL AND: COMPUTER EGINEERING . AMERICAN UNIVERSITY OF BEIRUT FALL TERM 2005-2006 MIDTERM ill " EECE~20 -DIGITAL SYTEMS DESIGN ( #: ,'- ~:ZOJ\tj!IY -KI-dabi ID:~Orooo~Y CO_URSESi,G110N: SECTION6& 3'(pROF. MANSOUR) INSTRUCTIONS: I 0 THE EXAM IS CLOSED BOOK/CLOSED NOTES. THE DURATION IS 2 HOURS. o CALCULATORS ARE NOT.ALLOWED. . o WRITE YOUR NAME ~ ID NUMBER IN THE SPACE PROVIDED AB,OVE. o INDICATE THE SECTION XOU ARE REGISTERED IN. o PROVIDE YOUR ANSWERS IN THE SPACE PROVIDED ON THE QUESTION SHEET. o THE SCRATCH BOOKLET wn.L NOT BE CONSIDERED IN GRADING. o BE AS NEAT AND CLEAR AS POSSIBLE. .., (0 ,:5& latch with enable usin" NAND !!ates. Show the corresponding function table of the latch. G}J o I I I ( S e ~d.d <:) (9 () I 10 / \ . (p,.}-Q, Lw.JQ.. C ( t I If tl b) Design a D latch with enable !isin!!NAND ~tes. show the corresponding function table of the latch. 5 G}..) . Solution: I: \ t \ Problem Total P.oints Earned'Points . l' 8 2 12 I 3 . 12 .-:;- 4 12 . . 1\ 5 12 ( 6 10 7 10 -::; 8 10 ').. 9 14 If)' Total 100 r;;J.J SI\. I 00 ) o I I 0 { { 0 I ( I [ ..fo u .s-.J.1... 1--;' CJ xx . ,]J CD :"'.,,,,,~@.,op ~mpl~Gcs . ~GZr . .. cJJ:; \9 K «<loo \0 (If ( I ' t, ~o ~j, '10 c b) Design a nef!attve edge triggered D flip-flop' USUtgSR latches with enable. Solution; .:-> -b . ::") . ./ . ...~ . Z-l =(fQ I (. @f. / "./ n~, + k. t') ...~ /\.\V . 'L .~. . \. )..,"- 0 '\ \ . .. ..::f;..~~(H \~ . ~ ~:. ..~ -/ l)~ \ \ .. l ,... 00 ~ ..::)",\ ~( "/01 <> O \.., I . \ ,",. \ / 0 I ."\. ,~/.. \U v':1\tI/W~' I ~ q b) Design a JK flip-flop using a-T flip-flop with enable. [3 points] Solution: - c) Design a positive edge triggered D flip-flop with ~vnchronous Dresetusing D latches with enable. Solotioo: <t. ../ d) Design a~ flip-flop with Test Input (Tl) and Te~t Enable (TE) using aDflip-tlip. Solution: . j , ! \ ~ . ."'" _\~ D .~_. ._- "vI ;. 0 ...Tf- o '\ 'T- 1'1 i O' \ . .. 1 "1---. !9.."/ Cv. ''f 0 ," ! V 1 I 6 \ CJ ( I c:J tft.,' ; j f< r . I c!, f. U I! J I l GJ '0 ' \ J I . l 1 I I j 6 :J.:..'.. ":'..:.. ; . '1. and outputs Q.. Q:. The characteristic equations of a "W;:~£esigna JKL flip-flop using JK flip-flops and ""';ij~i"K' Q;) :II+'L.(.YQ;~K'Q:) 'I ~"Z. .~ L- Ct-k.. . <9#.~ons sbown below. The inputs are I" 1:. 1,. I~ the ~;~;uI~puts clearly. "~"r.'.""."!:;. .. Solution: frC) s, So OC,) 6, 0-c 6) \ - ./ \ G \ ~;Z~. . .J!!Ii;igned serial comparator. The comparator compares two 8- ;~iS.one. if and only if A ~ B. The input bits of A and B .. .. _ d.cle:.U~i:rig:atf;~i(~QIParat.:,r. shift registers. and appropriate flip-flops. w;:seiiarcamparator: First' deSign the onc-bit comp'ai'ator. taking into accollllt how to use it to compare the nUmbers. Label all your inputs(oU1Puts, IUIitconnections clearly. Solution: ~ -=:> A o 6:: A/~1 +-A~/+ Ab ( o I ( c ~1'.~IC 11...$ '1 -\-I- j. \,<+ c..~..r h/ A o -"") b e"J.~ ~W~ ~-7 ..;.., IS cwpr; .-t etcxY' ~ CM.vk- ~ , cM cD [) ')1 {j'/ LJ .\ ;i ~ I ~ . :> <3 10 IU) IV I 0 I~ IL:~ ~ I() I 0 \ ~ t.o (} . <'~ ___I a 'a \-I ~IO~II ~,,( .- 11 d-d rO dOd -::: "'- cl 0. 01 ,- Id I!.-.Iq '"P .,...1 ,.. r C§) yie finite state machine with the following state transition diagram. It has a single input, IN, and iit;OUT. ' 0, 1/0 , i ~CJ(}DW1 1/1 a) Design a logic circuit that implements the MealY FSM using D. flip-flops; [5 points} Solution: - ~~ b(" S,-;r~ ~( t 5~1 of I,~ om . 50 1501°1 9'/.1 'I IW .~f JS'/I) SOt0 .\ DJ= :n/Ct>.,. 'j:}.)<G1 I ~ 7N ~;~()J .t our--:'ffi ll-! tJ r ' o Q' ( { .r 0 ~~. (V s o I> OVI // . -"',, b) Draw the state transition diagram for a Moore style fInite state 'machine with the same behavior. [4 points} Solution: " I 1lw}P& r>:J-~ I~ ~f oQ~J 0 I 1-.J Vv1 )" cV ;1 c) Design a logic circuit that implements the Moore FSM using D flip-flops. [5 points} Solutjon: J-IJ \ ~, c)\j "\ .6) ,IJ $I r D r ,Iat 60/0