EECE 320 Lecture 13, Fall 2011

EECE 320 L13: Combinational Logic design Practices 1 Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 13: Combinational Logic Design Practices Ali Chehab EECE 320 L13: Combinational Logic design Practices 2 Chehab, AUB, 2003 Generic Array Logic Devices (GALs)  GAL16V8 can be configured to emulate the AND-OR, flip-flop, and output structure of any of a variety of combinational and sequential PAL devices.  It can be electrically erased and reprogrammed  It has an XOR at the output with 1 input connected to ground via a fuse.  When the fuse is intact, it passes the output  When the fuse is blown, the input is high and inverts the output  The following figure shows the GAL16V8 configured as a combinational device similar to the PAL16V8 EECE 320 L13: Combinational Logic design Practices 3 Chehab, AUB, 2003 GAL16V8 EECE 320 L13: Combinational Logic design Practices 4 Chehab, AUB, 2003 Decoders  A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs.  In general, the input and output codes are different, and the output code has more bits than the input code.  There is a one-to-one mapping from input codewords to output codewords.  The most commonly used output code is the 1-out-of-m code where 1 bit is asserted at a time.  Ex: m=4, the 1-out-of-4 code has the codewords 0001, 0010, 0100, 1000 (active high)  For active low, the codewords are 1110, 1101, 1011, 0111  The n-bit code is typically used for the input  EX: n=3, the 8 codewords are 000, 001, …, 111 EECE 320 L13: Combinational Logic design Practices 5 Chehab, AUB, 2003 Binary Decoders (n-to-2n decoders)  The input is an n-bit binary code and the output is a 1 out-of-2n code.  It is not necessary to use all outputs of a decoder or to decode all possible input combinations. EECE 320 L13: Combinational Logic design Practices 6 Chehab, AUB, 2003 74x139 Dual 2-to-4 Decoder (MSI Part) EECE 320 L13: Combinational Logic design Practices 7 Chehab, AUB, 2003 74x138 3-to-8 Decoder EECE 320 L13: Combinational Logic design Practices 8 Chehab, AUB, 2003 74x138 3-to-8 Decoder EECE 320 L13: Combinational Logic design Practices 9 Chehab, AUB, 2003 Cascading Binary Decoders  Multiple binary decoders can be used to decode larger code words.  EX: using two 3-to-8 decoders to construct a 4-to-16 decoder.  When EN_L = 1, the decoder is inactive.  When EN_L = 0, the MSB bit N3 is used to select between the upper and lower decoders.  N3 = 0, select upper decoder  N3 = 1, select lower decoder  N2,N1,N0 select appropriate output within each decoder. EECE 320 L13: Combinational Logic design Practices 10 Chehab, AUB, 2003 Next Lecture and Reminders  Next lecture  Reminders