EECE 320 Lecture 16, Fall 2011

EECE 320 L16: Combinational Logic design Practices 1 Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 16: Combinational Logic Design Practices Ali Chehab EECE 320 L16: Combinational Logic design Practices 2 Chehab, AUB, 2003 Three-State Devices  Three-state buffers  If Enable line is asserted, the device acts like a normal buffer or inverter  If Enable is negated, the output “floats”: High Impedance (HI-Z) or in disconnected state  They allow multiple sources to share a single party line as long as 1 device talks on the line at one time. EN EECE 320 L16: Combinational Logic design Practices 3 Chehab, AUB, 2003 Three-State Devices EECE 320 L16: Combinational Logic design Practices 4 Chehab, AUB, 2003 74x541: 8 3-State Buffer Chip EECE 320 L16: Combinational Logic design Practices 5 Chehab, AUB, 2003 Using a 74x541 as a Microprocessor Input Port 8-bit bus read operation EECE 320 L16: Combinational Logic design Practices 6 Chehab, AUB, 2003 74x245: Bus Transceiver Enabling 2-Way Communication  A bus transceiver contains pairs of 3- state buffers connected in opposite directions so that data can be transferred in either direction.  A-to-B transfer: Dir = 1  B-to-A transfer: Dir = 0 EECE 320 L16: Combinational Logic design Practices 7 Chehab, AUB, 2003 Bidirectional Buses and Transceiver Operation EECE 320 L16: Combinational Logic design Practices 8 Chehab, AUB, 2003 Multiplexers  A multiplexer is a digital switch: It connects data from 1 of n sources to the output.  Cameras  Director  Screen  Registers  ALU  EX: 4-to-1 Multiplexer D0 D1 D2 D3 Z S1 S0 S1 S0 Z 0 0 D0 0 1 D1 1 0 D2 1 1 D3 Z = S1’.S0’.D0 + S1’.S0.D1 + S1.S0’.D2 + S1.S0.D3 EECE 320 L16: Combinational Logic design Practices 9 Chehab, AUB, 2003 Multiplexers EECE 320 L16: Combinational Logic design Practices 10 Chehab, AUB, 2003 74x151 8-Input, 1-Bit Multiplexer (A’.B’.C’.D0).EN_L’ (A.B’.C’.D1) .EN_L’ (A.B.C.D7) .EN_L’ D4 D5 D6 D7 Y C B D0 D1 D2 D3 Y_L A EN_L EECE 320 L16: Combinational Logic design Practices 11 Chehab, AUB, 2003 74x157 2-Input, 4-Bit Multiplexer S A[3:0] B[3:0] G_L Y[3:0] EECE 320 L16: Combinational Logic design Practices 12 Chehab, AUB, 2003 Expanding Multiplexers • 32-Input Mux • 5 select lines XA4 – XA0 • XA2, XA1, XA0 common • XA3, XA4  Decoder D31 XOUT X A 4 XEN_L D30 D29 D2 D1 D0 . . . X A 3 X A 2 X A 1 X A 0 EECE 320 L16: Combinational Logic design Practices 13 Chehab, AUB, 2003 Next Lecture and Reminders  Next lecture  Reminders