EECE 320 Syllabus, Fall 2011

American University of Beirut · Digital Systems Design · 2 pages · Dr. Lama Hamandi

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EECE 320 Syllabus, Fall 2011, page 1

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EECE 320 Syllabus, Fall 2011, page 2

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DIGITAL SYSTEMS DESIGN (EECE 320) Objective To learn the fundamental principles needed to analyze and design digital logic circuits, both combinational and sequential. The course focuses on digital design methodologies and the use of computer-aided design tools. Also the students will learn how to interpret and write documentation for digital circuits. Instructor Lama Hamandi Office: Bechtel Room 406D Office Hours: M, 12 – 2, W, 12 – 1, by appointment Email: lh13@aub.edu.lb Textbook  John F. Wakerly: “Digital Design Principles & Practices”, 4th Edition, Prentice-Hall, 2006. Prerequisite  EECE 210 Electric Circuits and Electronics Topics  Introduction (Ch. 1): Analog versus digital, Digital devices, Electronics and software aspects of digital design, Integrated circuits, Programmable logic devices, Application-specific ICs, Printed-circuit boards, Digital design levels, the name of the game. (self reading)  Number Systems and Codes (Ch. 2): Positional number systems, Octal and hexadecimal numbers, General positional number system conversions, Addition and subtraction of non decimal numbers, Representation of negative numbers, Two’s complement addition and subtraction, Binary codes for decimal numbers, Gray code.  Combinational Logic Design Principles (Ch. 4): Switching algebra, Combinational-circuit analysis, Combinational circuit synthesis, Programmed minimization methods, Timing hazards.  Hardware Description Languages (Ch. 5): The VHDL Hardware Description Language.  Combinational Logic Design Practices (Ch. 6): Circuit timing, PLDs, Decoder, Encoders, Multiplexers, Exclusive OR and parity circuits, Comparators, Adders, Subtractors and ALUs.  Sequential Logic Design Principles (Ch. 7): Latches and flip-flops, Clocked synchronous state machines, Designing state machines using state diagrams, VHDL sequential-circuit design features  Sequential Logic Design Practices (Ch. 8): Counters, Shift-registers.  Memory (ch. 9): Read-Only Memory, Read/Write Memory SRAM, DRAM Evaluation  Attendance, Assignments and drop quizzes 15%  Project (+ test) 15%  Midterm (Saturday December 3, 12pm, Wing D) 30%  Final Exam 40% Course Policy: 1. Homework is due in class at the beginning of the lecture. Late homework will be accepted with a penalty of 25% per day. You have to work individually on your homework. Similar homework will receive a grade of zero. 2. All lectures begin on the hour. Late students may be refused entry to the classroom. 3. Attendance of all lectures is required. Students who miss a lecture are responsible for its contents. 4. No makeup for drop quizzes and midterm. 5. Keep checking the class website (Moodle) for information and updates. 6. As per AUB policy, students who miss more than one fifth of the lectures in the first ten weeks of the semester may be dropped from the course. 7. Frequent absences: deduct up to 5% of your Final average 8. The project will be done in teams of two students. A test on the project material will be given at the end of the semester. A question in the Final exam will be asked about the project. Both students should be involved in all parts of the project in order to get a good grade. A copied project will get a grade of zero.