EECE 320 Lecture 14, Fall 2011

EECE 320 L14: Combinational Logic design Practices 1 Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 14: Combinational Logic Design Practices Ali Chehab EECE 320 L14: Combinational Logic design Practices 2 Chehab, AUB, 2003 2-to-4 Decoder in VHDL - Behavioral LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY decoder2to4 IS Port ( DATA: IN STD_LOGIC_VECTOR (1 DOWNTO 0) ; Y : OUT STD_LOGIC_VECTOR (0 TO 3) ) ; END decoder2to4 ; ARCHITECTURE behave OF decoder2to4 IS BEGIN PROCESS (DATA) BEGIN CASE DATA IS WHEN “00” => Y <= “1000” ; WHEN “01” => Y <= “0100” ; WHEN “10” => Y <= “0010” ; WHEN “11” => Y <= “0001” ; WHEN OTHERS => Y <= “0000” ; END CASE ; END PROCESS; END behave; EECE 320 L14: Combinational Logic design Practices 3 Chehab, AUB, 2003 3-to-8 Decoder in VHDL - Behavioral LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY V3to8dec IS Port ( G1, G2, G3 : IN STD_LOGIC ; A : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) ; Y : OUT STD_LOGIC_VECTOR(0 TO 7) ) ; END V3to8dec ; EECE 320 L14: Combinational Logic design Practices 4 Chehab, AUB, 2003 3-to-8 Decoder in VHDL - Behavioral ARCHITECTURE V3to8dec _b OF V3to8dec IS SIGNAL Y_s : STD_LOGIC_VECTOR(0 TO 7) ; BEGIN PROCESS(A, G1, G2, G3) BEGIN CASE A IS WHEN “000” => Y_s <= “10000000” ; WHEN “001” => Y_s <= “01000000” ; WHEN “010” => Y_s <= “00100000” ; WHEN “011” => Y_s <= “00010000” ; WHEN “100” => Y_s <= “00001000” ; WHEN“101” => Y_s <= “00000100” ; WHEN “110” => Y_s <= “00000010” ; WHEN “111” => Y_s <= “00000001” ; WHEN OTHERS => Y_s <= “00000000” ; END CASE ; IF (G1 AND G2 AND G3) = ‘1’ THEN Y <= Y_s ; ELSE Y <= “00000000” ; END IF ; END PROCESS; END V3to8dec _b; EECE 320 L14: Combinational Logic design Practices 5 Chehab, AUB, 2003 3-to-8 Decoder in VHDL – Data Flow ARCHITECTURE V3to8dec_a OF V3to8dec IS SIGNAL Y_s : STD_LOGIC_VECTOR(0 TO 7) ; BEGIN WITH A SELECT Y_s <= “10000000” WHEN “000” , “01000000” WHEN “001” , “00100000” WHEN “010” , “00010000” WHEN “011” , “00001000” WHEN “100” , “00000100” WHEN “101” , “00000010” WHEN “110” , “00000001” WHEN “111” , “00000000” WHEN OTHERS; Y <= Y_s WHEN (G1 AND G2 AND G3) = ‘1’ ELSE “00000000”; END V3to8dec _a; EECE 320 L14: Combinational Logic design Practices 6 Chehab, AUB, 2003 Encoders  The output code has fewer bits than the input code  The simplest encoder is the binary encoder (2n-to-n)  The input is a 1-out-of-2n code and the output is an n-bit binary code EECE 320 L14: Combinational Logic design Practices 7 Chehab, AUB, 2003 8-to-3 Encoder - Example  Y0 = I1 + I3 + I5 + I7  Y1 = I2 + I3 + I6 + I7  Y2 = I4 + I5 + I6 + I7 I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 EECE 320 L14: Combinational Logic design Practices 8 Chehab, AUB, 2003 Priority Encoders  If multiple inputs are asserted simultaneously, the binary encoder gives undesirable results  It is better to assign priorities to input lines  Highest priority line is serviced first  EX: 8-to-3 Priority Encoder with IDLE output - If no input is asserted, IDLE is asserted I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0 IDLE 1 x x x x x x x 1 1 1 0 0 1 x x x x x x 1 1 0 0 0 0 1 x x x x x 1 0 1 0 0 0 0 1 x x x x 1 0 0 0 0 0 0 0 1 x x x 0 1 1 0 0 0 0 0 0 1 x x 0 1 0 0 0 0 0 0 0 0 1 x 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 EECE 320 L14: Combinational Logic design Practices 9 Chehab, AUB, 2003 8-to-3 Priority Encoder  Intermediate Variables  H7 = I7 H6 = I6.I7’  H5 = I5.I6’.I5’ H4 = I4.I7’.I6’.I5’  H3 = I3. I7’.I6’.I5’.I4’ H2 = I2. I7’.I6’.I5’.I4’.I3’  H1 = I1. I7’.I6’.I5’.I4’.I3’.I2’ H0 = I0. I7’.I6’.I5’.I4’.I3’.I2’.I1’  Output Equations  A2 = H4 + H5 + H6 + H7  A1 = H2 + H3 + H6 + H7  A0 = H1 + H3 + H5 + H7  IDLE = (I0 + I1 + … + I7)’ = I0’.I1’. … .I7’ EECE 320 L14: Combinational Logic design Practices 10 Chehab, AUB, 2003 74x148 Priority Encoder  Inputs and Outputs are active low  GS asserted if EI asserted and 1 or more Inputs are asserted  EO asserted if EI is asserted but no input is asserted, could be connected to another EI (lower priority) EECE 320 L14: Combinational Logic design Practices 11 Chehab, AUB, 2003 Next Lecture and Reminders  Next lecture  Reminders