EECE 320 Lecture 10, Fall 2011

EECE 320 L10: VHDL 1 Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 10: VHDL Ali Chehab EECE 320 L10: VHDL 2 Chehab, AUB, 2003 XOR – Behavioral Architecture Library ieee; use ieee.std_logic_1164.all; entity myXOR is port (a, b : in std_logic; z : out std_logic); end myXOR; architecture behavioral of myXOR is begin comp : process (a, b) -- sensitivity list begin if a /= b then z <= ‘1’; else z <= ‘0’; end if; end process comp; end behavioral; EECE 320 L10: VHDL 3 Chehab, AUB, 2003 XOR – Data-Flow Architecture library ieee; use ieee.std_logic_1164.all; entity myXOR is port (a, b : in std_logic; z : out std_logic); end myXOR; architecture dataflow1 of myXOR is begin z <= ‘1’ when (a /= b) -- “when” concurrent statement else ‘0’ ; end dataflow1; architecture dataflow2 of myXOR is begin z <= ((not a) and b) or (a and (not b)); -- SOP = a’.b + a.b’ end dataflow2; EECE 320 L10: VHDL 4 Chehab, AUB, 2003 XOR – Structural Architecture EECE 320 L10: VHDL 5 Chehab, AUB, 2003 XOR – Structural Architecture -- File: myAND.vhd library ieee; use ieee.std_logic_1164.all; entity myAND is port (a, b : in std_logic; c : out std_logic); end myAND; architecture arch_AND of myAND is begin c <= a and b ; end arch_AND; EECE 320 L10: VHDL 6 Chehab, AUB, 2003 XOR – Structural Architecture -- File: myOR.vhd library ieee; use ieee.std_logic_1164.all; entity myOR is port (a, b : in std_logic; c : out std_logic); end myOR; architecture arch_OR of myOR is begin c <= a or b ; end arch_OR; EECE 320 L10: VHDL 7 Chehab, AUB, 2003 XOR – Structural Architecture library ieee; use ieee.std_logic_1164.all; entity myXOR is port (a, b : in std_logic; c : out std_logic); end myXOR; architecture struct of myXOR is component myAND port (a, b : in std_logic; c : out std_logic); end component; component myOR port (a, b : in std_logic; c : out std_logic); end component; EECE 320 L10: VHDL 8 Chehab, AUB, 2003 XOR – Structural Architecture signal na, nb, aout1, aout2 : std_logic; begin na <= not a; nb <= not b; u0: myAND port map (na, b, aout1); u1: myAND port map (a, nb, aout2); u2: myOR port map (aout1, aout2, c); end struct; EECE 320 L10: VHDL 9 Chehab, AUB, 2003 Generate Statement – 8-bit Inverter Library IEEE; Use ieee.std_logic_1164.all; Entity inv8 is port (x : in STD_LOGIC_VECTOR(1 to 8); y : out STD_LOGIC_VECTOR(1 to 8) ); End inv8; Architecture inv8_arch of inv8 is Component INV port (I : in STD_LOGIC; O : out STD_LOGIC); End component; Begin g1: for b in 1 to 8 generate U1: INV port map ( x(b) , y(b) ); end generate; End inv8_arch; EECE 320 L10: VHDL 10 Chehab, AUB, 2003 Generic Declaration – Bus Inverter Library IEEE; Use ieee.std_logic_1164.all; Entity businv is generic (WIDTH : positive); port (x : in STD_LOGIC_VECTOR(WIDTH-1 downto 0); y : out STD_LOGIC_VECTOR(WIDTH-1 downto 0) ); End businv; Architecture businv_arch of businv is Component INV port (I : in STD_LOGIC; O : out STD_LOGIC); End component; Begin g1: for b in WIDTH-1 downto 0 generate U1: INV port map ( x(b) , y(b) ); end generate End businv_arch ; -- CALL: U1: businv generic map(WIDTH=>8) port map (in8, out8); EECE 320 L10: VHDL 11 Chehab, AUB, 2003 Time Dimension and Simulation  A time delay can be introduced using “after” or “wait”. Z <= ‘1’ after 4 ns when x=‘1’ and ‘y’=0 else ‘0’ after 3 ns; entity InhinitTB is end InhinitTB; architecture InhibitTB_arch of InhibitTB is component Inhibit port (x,y : in BIT; z : out BIT); end component; signal xt, yt, zt : BIT; begin U1: Inhibit port map ( xt , yt, zt ); process begin xt <= ‘0’; yt <= ‘0’; wait for 10 ns; xt <= ‘0’; yt <= ‘1’; wait for 10 ns; xt <= ‘1’; yt <= ‘0’; wait for 10 ns; xt <= ‘1’; yt <= ‘1’; wait for 10 ns; wait; ------------------------------------- suspend process forever; end process; end InhibitTB_arch; EECE 320 L10: VHDL 12 Chehab, AUB, 2003 Functions  A VHDL function accepts a number of arguments and returns a result function function_name ( signal-names: signal-type; … signal-names: signal-type ) return return-type is type declarations constant declarations variable declarations function definitions Procedure definitions begin sequential-statement … sequential-statement end function_name architecture MyArchitecture of BlackBox is function ButNot (A, B: bit) return bit is begin if B = ‘1’ then return A; else return ‘0’; end if; end ButNot; begin Z <= ButNot(X,Y); end MyArchitecture ; -- Example EECE 320 L10: VHDL 13 Chehab, AUB, 2003 Function: convert standard logic vector to integer function CONV_INTEGER (X: STD_LOGIC_VECTOR) return INTEGER is variable RESULT: INTEGER; begin RESULT := 0; for i in X'range loop RESULT := RESULT * 2; case X(i) is when '0' | 'L' => null; when '1' | 'H' => RESULT := RESULT + 1; when others => null; end case; end loop; return RESULT; end CONV_INTEGER; EECE 320 L10: VHDL 14 Chehab, AUB, 2003 Function: convert integer to standard logic vector function CONV_STD_LOGIC_VECTOR(arg: integer; size: integer) return std_logic_vector is variable result : std_logic_vector(size-1 downto 0); variable temp : integer; begin temp := arg; for i in 0 to size-1 loop if (temp mod 2) = 1 then result(i) := '1'; else result(i) := '0'; end if; temp := temp/2; end loop; return result; end; EECE 320 L10: VHDL 15 Chehab, AUB, 2003 Libraries and Packages  A VHDL library is a place where VHDL compiler stores info and intermediate files about a project  For a given design, compiler creates and automatically uses the library ‘’work’’  Including the IEEE library:  library ieee;  A VHDL package is a file containing definitions of objects that can be used in other programs  EX: signal, constant, type, function, procedure, component declarations  A design can ‘use’ a package by including a use clause  EX: To use all definitions in the IEEE standard 1164 package:  Write: use ieee.std_logic_1164.all;  Within the ieee library, the file std_logic_1164 contains the desired definitions  The suffix “all” tells the compiler to use all definitions  A user can create custom packages EECE 320 L10: VHDL 16 Chehab, AUB, 2003 1-bit Full Adder library IEEE; use IEEE.std_logic_1164.all; entity full_adder is port ( X: in STD_LOGIC; Y: in STD_LOGIC; CIN: in STD_LOGIC; S: out STD_LOGIC; COUT: out STD_LOGIC ); end full_adder; architecture full_adder of full_adder is begin S <= (X XOR Y) XOR CIN ; COUT <= (X AND Y) OR (X AND CIN) OR (Y AND CIN); end full_adder; FullAdder 1 Bit X Y S CIN COUT EECE 320 L10: VHDL 17 Chehab, AUB, 2003 1-bit Full Adder - Testbench library ieee; use ieee.std_logic_1164.all; entity full_adder_tb is end full_adder_tb; architecture TB_ARCHITECTURE of full_adder_tb is component full_adder port ( X : in std_logic; Y : in std_logic; CIN : in std_logic; S : out std_logic; COUT : out std_logic ); end component; signal X : std_logic := '0'; signal Y : std_logic := '0'; signal CIN : std_logic := '0'; signal S : std_logic; signal COUT : std_logic; EECE 320 L10: VHDL 18 Chehab, AUB, 2003 1-bit Full Adder - Testbench begin UUT : full_adder port map (X => X, Y => Y, CIN => CIN, S => S, COUT => COUT ); CIN <= NOT CIN after 10 ns; Y <= NOT Y after 20 ns; X <= NOT X after 40 ns; end TB_ARCHITECTURE; EECE 320 L10: VHDL 19 Chehab, AUB, 2003 1-bit Full Adder - Simulation X Y CIN S COUT ns 20 40 60 80 EECE 320 L10: VHDL 20 Chehab, AUB, 2003 Structural 4-Bit Full Adder CIN0 X(0) Y(0) S(0) COUT(1) CIN S X Y COUT X(1) Y(1) S(1) COUT(2) CIN S X Y COUT X(2) Y(2) S(2) COUT(3) CIN S X Y COUT X(3) Y(3) S(3) COUT4 CIN S X Y COUT EECE 320 L10: VHDL 21 Chehab, AUB, 2003 4-bit Adder library IEEE; use IEEE.std_logic_1164.all; entity adder4b is port ( X : in STD_LOGIC_VECTOR(3 downto 0); Y : in STD_LOGIC_VECTOR(3 downto 0); C0: in STD_LOGIC; S : out STD_LOGIC_VECTOR(3 downto 0); C4: out STD_LOGIC ); end adder4b; EECE 320 L10: VHDL 22 Chehab, AUB, 2003 4-bit Adder architecture adder4b of adder4b is component full_adder port ( X : in STD_LOGIC; Y : in STD_LOGIC; CIN : in STD_LOGIC; S : out STD_LOGIC; COUT: out STD_LOGIC ); end component; signal C : std_logic_vector(1 to 3); begin U1: full_adder port map (X=>X(0), Y=>Y(0), CIN=> C0, S=>S(0), COUT=>C(1)); U2: full_adder port map (X=>X(1), Y=>Y(1), CIN=> C(1), S=>S(1), COUT=>C(2)); U3: full_adder port map (X=>X(2), Y=>Y(2), CIN=> C(2), S=>S(2), COUT=>C(3)); U4: full_adder port map (X=>X(3), Y=>Y(3), CIN=> C(3), S=>S(3), COUT=>C4); end adder4b EECE 320 L10: VHDL 23 Chehab, AUB, 2003 4-bit Adder - Testbench library ieee; use ieee.std_logic_1164.all; entity adder4b_tb is end adder4b_tb; architecture TB_ARCHITECTURE of adder4b_tb is component adder4b port ( X : in std_logic_vector(3 downto 0); Y : in std_logic_vector(3 downto 0); C0 : in std_logic; S : out std_logic_vector(3 downto 0); C4 : out std_logic ); end component; signal X : std_logic_vector(3 downto 0) := "0000"; signal Y : std_logic_vector(3 downto 0) := "0000"; signal C0 : std_logic := '0'; signal S : std_logic_vector(3 downto 0); signal C4 : std_logic; EECE 320 L10: VHDL 24 Chehab, AUB, 2003 4-bit Adder - Testbench begin UUT : adder4b port map (X => X, Y => Y, C0 => C0, S => S, C4 => C4); process begin X <= "0000"; wait for 10 ns; Y <= "0001"; wait for 10 ns; X <= "0010"; wait for 10 ns; Y <= "0011"; wait for 10 ns; X <= "0100"; wait for 10 ns; Y <= "0101"; wait for 10 ns; X <= "0110"; wait for 10 ns; Y <= "0111"; wait for 10 ns; X <= "1000"; wait for 10 ns; Y <= "1001"; wait for 10 ns; X <= "1010"; wait for 10 ns; Y <= "1011"; wait for 10 ns; X <= "1100"; wait for 10 ns; Y <= "1101"; wait for 10 ns; X <= "1110"; wait for 10 ns; Y <= "1111"; wait for 10 ns; wait; end process; end TB_ARCHITECTURE; EECE 320 L10: VHDL 25 Chehab, AUB, 2003 4-bit Adder - Simulation X Y C0 S C4 0 0 1 0 3 1 5 2 7 3 9 4 B 5 D 6 F 7 1 8 3 9 5 A 7 B 9 B C D E F D ns 20 40 60 80 100 120 140 EECE 320 L10: VHDL 26 Chehab, AUB, 2003 16-bit Adder library IEEE; use IEEE.std_logic_1164.all; entity adder16b is port ( X : in STD_LOGIC_VECTOR(15 downto 0); Y : in STD_LOGIC_VECTOR(15 downto 0); C0 : in STD_LOGIC; S : out STD_LOGIC_VECTOR(15 downto 0); C16: out STD_LOGIC ); end adder16b; EECE 320 L10: VHDL 27 Chehab, AUB, 2003 16-bit Adder architecture adder16b of adder16b is component full_adder port ( X : in STD_LOGIC; Y : in STD_LOGIC; CIN : in STD_LOGIC; S : out STD_LOGIC; COUT: out STD_LOGIC ); end component; signal C : std_logic_vector(0 to 16); begin g1: for b in 0 to 15 generate U1: full_adder port map (X=>X(b), Y=>Y(b), CIN=> C(b), S=>S(b), COUT=>C(b+1)); end generate; C(0) <= C0; C16 <= C(16); end adder16b; EECE 320 L10: VHDL 28 Chehab, AUB, 2003 16-bit Adder - Testbench library ieee; use ieee.std_logic_1164.all; entity adder16b_tb is end adder16b_tb; architecture TB_ARCHITECTURE of adder16b_tb is component adder16b port( X : in std_logic_vector(15 downto 0); Y : in std_logic_vector(15 downto 0); C0 : in std_logic; S : out std_logic_vector(15 downto 0); C16 : out std_logic ); end component; signal X : std_logic_vector(15 downto 0) := (others => '0'); signal Y : std_logic_vector(15 downto 0) := (others => '0'); signal C0 : std_logic := '0'; signal S : std_logic_vector(15 downto 0); signal C16 : std_logic; EECE 320 L10: VHDL 29 Chehab, AUB, 2003 16-bit Adder - Testbench begin UUT : adder16b port map (X => X, Y => Y, C0 => C0, S => S, C16 => C16 ); process begin X <= "0000000000000000"; wait for 10 ns; Y <= "0000000000000001"; wait for 10 ns; X <= "0000000000000010"; wait for 10 ns; Y <= "0000000000000011"; wait for 10 ns; X <= "0000000000000100"; wait for 10 ns; Y <= "0000000000000101"; wait for 10 ns; X <= "0000000000000110"; wait for 10 ns; Y <= "0000000000000111"; wait for 10 ns; X <= "0000000000001000"; wait for 10 ns; Y <= "0000000000001001"; wait for 10 ns; X <= "0000000000001010"; wait for 10 ns; Y <= "0000000000001011"; wait for 10 ns; X <= "0000000000001100"; wait for 10 ns; Y <= "0000000000001101"; wait for 10 ns; X <= "0000000000001110"; wait for 10 ns; Y <= "0000000000001111"; wait for 10 ns; wait; end process; end TB_ARCHITECTURE; EECE 320 L10: VHDL 30 Chehab, AUB, 2003 16-bit Adder - Simulation X Y C0 S C16 0000 0000 0001 0000 0003 0001 0005 0002 0007 0003 0009 0004 000B 0005 000D 000F 0006 0007 0008 0009 0011 ns 10 20 30 40 50 60 70 80 90 EECE 320 L10: VHDL 31 Chehab, AUB, 2003 Next Lecture and Reminders  Next lecture  Reminders