EECE 320 Lecture 19, Fall 2011

EECE 320 L19: Combinational Logic design Practices 1 Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 19: Sequential Logic Design Principles Ali Chehab EECE 320 L19: Combinational Logic design Practices 2 Chehab, AUB, 2003 D latch: 1-Bit Memory EECE 320 L19: Combinational Logic design Practices 3 Chehab, AUB, 2003 D Latch: Timing Parameters  There is a window around the falling edge of C where D must not chage. This window consists of Setup time and Hold time.  A violation of the Setup time or Hold time can lead to Metastability EECE 320 L19: Combinational Logic design Practices 4 Chehab, AUB, 2003 Edge-Triggered D Flip-Flop  Pair of D latches: Master and Slave  If CLK = 0, Master is Open, Slave is Closed  If CLK = 1, Master is Closed, Slave is Open EECE 320 L19: Combinational Logic design Practices 5 Chehab, AUB, 2003 Timing Behavior of a Positive-edge-triggered D Flip-flop  Setup/Hold window: Input D is not supposed to change  Otherwise: Oscillate, metastable, unpredictable 0/1 state EECE 320 L19: Combinational Logic design Practices 6 Chehab, AUB, 2003 Negative-Edge-Triggered D Flip-Flop EECE 320 L19: Combinational Logic design Practices 7 Chehab, AUB, 2003 D Flip-Flop With Preset & Clear  PR and CLR are asynchronous inputs that Preset and Clear Q independently of the D and CLK inputs. They are mainly useful for initialization and testing purposes. 0 1 0 1 0 1 1 1 0 1 1 0 EECE 320 L19: Combinational Logic design Practices 8 Chehab, AUB, 2003 Next Lecture and Reminders  Next lecture  Reminders