EECE 320 Lecture 20, Fall 2011

EECE 320 L20: Combinational Logic design Practices 1 Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 20: Sequential Logic Design Principles Ali Chehab EECE 320 L20: Combinational Logic design Practices 2 Chehab, AUB, 2003 Positive-Edge D Flip-Flop With Enable  If EN = 1, New value of D is selected as input to Flip-Flop  If EN = 0, old value of D is selected => retained. EECE 320 L20: Combinational Logic design Practices 3 Chehab, AUB, 2003 ASIC Testing Using Scan Chain L O G I C SCAN IN SCAN OUT SCAN Flip-Flops Input Pins Output Pins  ASIC: Application-Specific Integrated Circuit  An important flip-flop function for ASIC testing is scan capability.  Idea: Drive the D input with an alternate source of data during testing EECE 320 L20: Combinational Logic design Practices 4 Chehab, AUB, 2003 Scan Flip-Flop/Chain  D Flip-Flop with a 2-input multiplexer  If TE is asserted (testing mode) TI is input to Flip-Flop  If TE is negated (normal mode) D is input to Flip-Flop EECE 320 L20: Combinational Logic design Practices 5 Chehab, AUB, 2003 Edge-Triggered J-K Flip-Flop  At Rising Edge of CLK, Next_Q = J.Q’ + K’.Q  J-K eliminates the problem of asserting both inputs EECE 320 L20: Combinational Logic design Practices 6 Chehab, AUB, 2003 T Flip-Flop  T (toggle) Flip-Flop changes state on every tick of the clock  Frequency of Q = half that of T T using D T using J-K EECE 320 L20: Combinational Logic design Practices 7 Chehab, AUB, 2003 T With Enable EECE 320 L20: Combinational Logic design Practices 8 Chehab, AUB, 2003 Clocked Synchronous State Machine Analysis  General Structure (Mealy Machine)  Next State = F(current state, input)  Output = G(current state, input) EECE 320 L20: Combinational Logic design Practices 9 Chehab, AUB, 2003 Clocked Synchronous State Machine Analysis  General Structure (Moore Machine)  Next State = F(current state, input)  Output = G(current state)  Output-coded state assignment = Moore machine with output logic consisting of just wires: Outputs available immediately and don’t change during each clock period