EECE 320 Lecture 27, Fall 2011

EECE 320 L27: Combinational Logic design Practices 1 Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 27: Sequential Logic Design Principles Ali Chehab EECE 320 L27: Combinational Logic design Practices 2 Chehab, AUB, 2003 S-R Latch in VHDL library IEEE; use ieee.std_logic_1164.all; entity SR_latch is port (S, R : in std_logic; Q, QN: buffer std_logic); end SR_latch; architecture SR_arch of SR_latch is begin QN <= S NOR Q; Q <= R NOR QN; end SR_arch; If you don’t want to use buffer? EECE 320 L27: Combinational Logic design Practices 3 Chehab, AUB, 2003 D Flip-Flop in VHDL library IEEE; use ieee.std_logic_1164.all; entity DFF is port (CLK, CLR, D: in std_logic; Q, QN: out std_logic); end DFF; architecture DFF_arch of DFF is begin process (CLK, CLR) begin if CLR = ‘1’ then -- Asynchronous RESET Q <= ‘0’; QN <= ‘1’; elsif CLK’event AND CLK = ‘1’ then -- Rising Edge of CLK Q <= D; QN <= NOT D; end if; end process; end DFF_arch; Synchronous Reset? EECE 320 L27: Combinational Logic design Practices 4 Chehab, AUB, 2003 Designing Finite State Machines S0 S1 S2 S3 X = 1 X = 1 X = 1 X = 1 / st_out = 1 X = 0 X = 0 X = 0 X = 0 EECE 320 L27: Combinational Logic design Practices 5 Chehab, AUB, 2003 VHDL: FSM Design entity test is port ( X, clock: in bit; st_out : out bit); end test; architecture arch_test of test is type state is (S0, S1, S2, S3); signal current_state, next_state: state; begin Comb_logic: process ( current_state, X) begin case current_state is when S0 => if X = ‘0’ then st_out <= ‘0’ next_state <= S0; else st_out <= ‘0’ next_state <= S1; end if; EECE 320 L27: Combinational Logic design Practices 6 Chehab, AUB, 2003 VHDL: FSM Design when S1 => if X = ‘0’ then st_out <= ‘0’; next_state <= S1; else st_out <= ‘0’; next_state <= S2; end if; when S2 => if X = ‘0’ then st_out <= ‘0’; next_state <= S2; else st_out <= ‘0’ next_state <= S3; end if; when S3 => if X = ‘0’ then st_out <= ‘0’; next_state <= S3; else st_out <= ‘1’; next_state <= S0; end if; end case; end process; EECE 320 L27: Combinational Logic design Practices 7 Chehab, AUB, 2003 VHDL: FSM Design seq: process -- no sensitivity list because of “wait” begin wait until clock’event and clock = ‘1’; current_state <= next_state; end process; end arch_test; EECE 320 L27: Combinational Logic design Practices 8 Chehab, AUB, 2003 FSM in VHDL: FORD Tail Lights EECE 320 L27: Combinational Logic design Practices 9 Chehab, AUB, 2003 FSM in VHDL: FORD Tail Lights library IEEE; use IEEE.std_logic_1164.all; entity Ford_Lights is port ( CLK: in STD_LOGIC; HAZ: in STD_LOGIC; RIGHT: in STD_LOGIC; LEFT: in STD_LOGIC; RA: out STD_LOGIC; RB: out STD_LOGIC; RC: out STD_LOGIC; LA: out STD_LOGIC; LB: out STD_LOGIC; LC: out STD_LOGIC ); end Ford_Lights; EECE 320 L27: Combinational Logic design Practices 10 Chehab, AUB, 2003 FSM in VHDL: FORD Tail Lights architecture Ford_Lights of Ford_Lights is type my_states is (IDLE, L1, L2, L3, R1, R2, R3, LR3); signal P_STATE, N_STATE: my_states := IDLE; begin SEQ: process(CLK) begin if CLK'event AND CLK = '1' then P_STATE <= N_STATE; end if; end process SEQ; EECE 320 L27: Combinational Logic design Practices 11 Chehab, AUB, 2003 FSM in VHDL: FORD Tail Lights COMB: process(P_STATE, HAZ, LEFT, RIGHT) begin RA <= '0'; RB <= '0'; RC <= '0'; LA <= '0'; LB <= '0'; LC <= '0'; case P_STATE is when IDLE => if LEFT = '0' AND RIGHT = '0' AND HAZ = '0' then N_STATE <= IDLE; elsif HAZ = '1' OR (LEFT = '1' AND RIGHT = '1') then N_STATE <= LR3; RA <= '1'; RB <= '1'; RC <= '1'; LA <= '1'; LB <= '1'; LC <= '1'; elsif LEFT = '1' AND RIGHT = '0' AND HAZ = '0' then N_STATE <= L1; LA <= '1'; elsif LEFT = '0' AND RIGHT = '1' AND HAZ = '0' then N_STATE <= R1; RA <= '1'; end if; EECE 320 L27: Combinational Logic design Practices 12 Chehab, AUB, 2003 FSM in VHDL: FORD Tail Lights when L1 => if HAZ = '1' then N_STATE <= LR3; RA <= '1'; RB <= '1'; RC <= '1'; LA <= '1'; LB <= '1'; LC <= '1'; elsif HAZ = '0' then N_STATE <= L2; LA <= '1'; LB <= '1'; end if; when L2 => if HAZ = '1' then N_STATE <= LR3; RA <= '1'; RB <= '1'; RC <= '1'; LA <= '1'; LB <= '1'; LC <= '1'; elsif HAZ = '0' then N_STATE <= L3; LA <= '1'; LB <= '1'; LC <= '1'; end if; EECE 320 L27: Combinational Logic design Practices 13 Chehab, AUB, 2003 FSM in VHDL: FORD Tail Lights when L3 => N_STATE <= IDLE; when R1 => if HAZ = '1' then N_STATE <= LR3; RA <= '1'; RB <= '1'; RC <= '1'; LA <= '1'; LB <= '1'; LC <= '1'; elsif HAZ = '0' then N_STATE <= R2; RA <= '1'; RB <= '1'; end if; when R2 => if HAZ = '1' then N_STATE <= LR3; RA <= '1'; RB <= '1'; RC <= '1'; LA <= '1'; LB <= '1'; LC <= '1'; elsif HAZ = '0' then N_STATE <= R3; RA <= '1'; RB <= '1'; RC <= '1'; end if; EECE 320 L27: Combinational Logic design Practices 14 Chehab, AUB, 2003 FSM in VHDL: FORD Tail Lights when R3 => N_STATE <= IDLE; when LR3 => N_STATE <= IDLE; end case; end process; end Ford_Lights; CLK HAZ LEFT LA LB LC RIGHT RA RB RC ns 20 40 60 80 100 120 140 160 180 200 220 EECE 320 L27: Combinational Logic design Practices 15 Chehab, AUB, 2003 FORD Tail Lights: Outputs Registered