EECE 320 Lecture 3, Fall 2011

EECE 320 L3: Combinational Logic design Principles 1 Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 3: Combinational Logic Design Principles Ali Chehab EECE 320 L3: Combinational Logic design Principles 2 Chehab, AUB, 2003 Combinational Circuit  The outputs of the circuit depend only on its current inputs  Example: Mechanical TV channel selector  The outputs of a sequential circuit depend not only on current inputs but also on past sequence of inputs  Example: Up/Down channel buttons of a TV remote control  A combinational circuit contains any number of gates but no feedback loops  Otherwise, sequential behavior  A combinational circuit may have 1 or more outputs EECE 320 L3: Combinational Logic design Principles 3 Chehab, AUB, 2003 Switching Algebra (Boolean)  Axioms (definitions that are assumed to be true)  A variable X can take 1 of 2 values  (A1) X = 0 if X  1 (A1’) X = 1 if X  0  An inverter is a logic circuit with output = opposite of input designated with prime (‘), or designated as NOT  (A2) if X = 0, then X’ = 1 (A2’) if X = 1, then X’ = 0 X Y = X’ 0 1 1 0 Truth Table Or Y = NOT X EECE 320 L3: Combinational Logic design Principles 4 Chehab, AUB, 2003 Switching Algebra (Boolean)  An AND gate produces a 1 if and only if all its inputs = 1 Or Z = X AND Y X Y X.Y 0 0 0 0 1 0 1 0 0 1 1 1  An OR gate produces a 1 if one or more inputs = 1 Or Z = X OR Y X Y X+Y 0 0 0 0 1 1 1 0 1 1 1 1 EECE 320 L3: Combinational Logic design Principles 5 Chehab, AUB, 2003 Switching Algebra (Boolean)  A NAND gate produces a 0 if and only if all its inputs = 1 X Y (X.Y)’ 0 0 1 0 1 1 1 0 1 1 1 0  A NOR gate produces a 0 if one or more inputs = 1 X Y (X+Y)’ 0 0 1 0 1 0 1 0 0 1 1 0 Z = X NAND Y Z = X NOR Y EECE 320 L3: Combinational Logic design Principles 6 Chehab, AUB, 2003 Switching Algebra (Boolean)  (A3) 0.0 = 0 (A3’) 1 + 1 = 1  (A4) 1.1 = 1 (A4’) 0 + 0 = 0  (A5) 0.1 = 1.0 = 0 (A5’) 1 + 0 = 0 + 1 = 1  All other facts of switching algebra can be proven using (A1) -(A5) and (A1’) – (A5’) EECE 320 L3: Combinational Logic design Principles 7 Chehab, AUB, 2003 Switching Algebra (Boolean)  Single Variable Theorems  (T1) X + 0 = X (T1’) X . 1 = X (Identities)  (T2) X + 1 = 1 (T2’) X . 0 = 0 (Null elements)  (T3) X + X = X (T3’) X . X = X (Idempotency)  (T4) (X’)’ = X (Involution)  (T5) X + X’ = 1 (T5’) X . X’ = 0 (Complements)  We can prove them by perfect induction  Prove them to be true for X=0 and for X=1  EX: (T1) If X = 0  0 + 0 = 0 = X  If X = 1  1 + 0 = 1 = X EECE 320 L3: Combinational Logic design Principles 8 Chehab, AUB, 2003 Switching Algebra (Boolean)  Two and Three-variable Theorems  (T6) X + Y = Y + X (T6’) X . Y = Y.X (Commutativity)  (T7) (X + Y) + Z = X + (Y + Z)  (T7’) (X .Y).Z = X.(Y.Z) (Associativity)  (T8) X.Y + X.Z = X.(Y+Z)  (T8’) (X+Y).(X+Z) = X + Y.Z (Distributivity)  (T9) X + X.Y = X  (T9’) X.(X+Y) = X (Covering)  (T10) X.Y + X.Y’ = X  (T10’) (X+Y).(X+Y’) = X (Combining)  (T11) X.Y + X’.Z + Y.Z = X.Y + X’.Z  (T11’) (X+Y).(X’+Z).(Y+Z) = (X+Y).(X’+Z) (Consensus)  The consensus terms can be removed in both cases of being = 0 or =1 EECE 320 L3: Combinational Logic design Principles 9 Chehab, AUB, 2003 Switching Algebra (Boolean)  N-variable Theorems  Can be proven by finite induction - True for N=2 - If true for i, prove for i+1  (T12) X+X+ … +X = X  (T12’) X.X. … .X = X (Generalized Idempotency)  (T13) (X1.X2. … .XN)’ = X1’+X2’+ … +XN’  (T13’) (X1+X2+ … +XN)’ = X1’.X2’. … .XN’ (De Morgan) EECE 320 L3: Combinational Logic design Principles 10 Chehab, AUB, 2003 Switching Algebra (Boolean)  (Generalized De Morgan’s Theorems)  (T14) [F(X1, X2, …, XN, +, .)]’ = F(X1’, X2’, …, XN’, ., +)  EX: [(W’.Z)+(X.Y)+(W.(X’+Z’))]’ = (W+Z’).(X’+Y’).(W’+(X.Z)) EECE 320 L3: Combinational Logic design Principles 11 Chehab, AUB, 2003 Switching Algebra (Boolean)  (Shanon Expansions Theorems)  (T15) F(X1, X2, …, XN) = X1. F(1, X2, …, XN) + X1’. F(0, X2, …, XN)  (T15’) F(X1, X2, …, XN) = [X1+F(0, X2, …, XN)].[X1’+F(1, X2, …, XN)]  Shanon is useful when trying to do implementations with muxes  Example: F(X,Y,Z) = XYZ’ + Y.(X+Z)+X’Y’Z’ F(1,Y,Z) = YZ’+Y=Y, F(0,Y,Z) = YZ+Y’Z’ => F(X,Y,Z) = XY + X’(YZ+Y’Z’) F(1,X2,..,XN) F(0,X2,..,XN) X1 (select) F(X1,X2,..,XN) EECE 320 L3: Combinational Logic design Principles 12 Chehab, AUB, 2003 Next Lecture and Reminders  Next lecture  Reminders