EECE 320 Lecture 30, Fall 2011
American University of Beirut · Digital Systems Design · 9 pages · Prof. Ali Chehab
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EECE 320 L30: Finite State Machine Examples 1
Chehab, AUB, 2003
EECE 320
Digital Systems Design
Lecture 30
Finite State Machines
Examples
Ali Chehab
EECE 320 L30: Finite State Machine Examples 2
Chehab, AUB, 2003
Modulo-10 Counter Using T FFs
The counter will go through the sequence: 0000, 0001, 0010, 0011, 0100,
0101, 0110, 0111, 1000, 1001, 000, …
A3 A2 A1 A0
A3 A2 A1 A0
E3 E2 E1 E0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
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1
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0
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1
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0
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0
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Present State Next State Excitations
EECE 320 L30: Finite State Machine Examples 3
Chehab, AUB, 2003
Modulo-10 Counter Using T FFs (Min Risk)
1
1
0
0
10
1
1
1
0
11
1
1
0
0
01
0
1
0
0
00
10
11
01
00
A3A2
A1A0
E3 = A3A2+A3A0+A3A1+A2A1A0
A3A2
0
1
0
0
10
0
1
1
1
11
0
1
0
0
01
0
1
0
0
00
10
11
01
00
A1A0
E2 = A3A2+A’3A1A0
1
1
0
0
10
1
1
1
1
11
0
0
1
1
01
0
0
0
0
00
10
11
01
00
A3A2
A1A0
E1 = A’3A0+A3A1
0
0
1
1
10
1
1
1
1
11
1
1
1
1
01
1
0
1
1
00
10
11
01
00
A3A2
A1A0
E0 = A’3+A0+A’2A’1
EECE 320 L30: Finite State Machine Examples 4
Chehab, AUB, 2003
Modulo-10 Counter Using T FFs (Min Risk)
T
E0
A0
T
E1
A1
T
E2
A2
T
E3
A3
CLK
A3
A2
A3
A0
A3
A1
A2
A1
A0
A3
A1
A’3
A1
A0
A’3
A0
A3
A1
A’2
A’1
A’3
A0
EECE 320 L30: Finite State Machine Examples 5
Chehab, AUB, 2003
Modulo-10 Counter Using T FFs - VHDL
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_unsigned.all;
entity count10 is
port (
CLK: in STD_LOGIC;
CLR: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR (3 downto 0)
);
end count10;
EECE 320 L30: Finite State Machine Examples 6
Chehab, AUB, 2003
Modulo-10 Counter Using T FFs - VHDL
architecture count10 of count10 is
signal IQ: std_logic_vector(3 downto 0);
begin
process (CLK, IQ)
begin
if (CLK'event and CLK = '1') then
if CLR = '1' then
IQ <= (others => '0');
elsif (IQ = 9) then
IQ <= "0000";
else
IQ <= IQ + 1;
end if;
end if;
Q <= IQ;
end process;
end count10;
EECE 320 L30: Finite State Machine Examples 7
Chehab, AUB, 2003
Modulo-10 Counter Using T FFs - VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity count10_tb is
end count10_tb;
architecture count10_tb of count10_tb is
component count10
port (
CLK: in STD_LOGIC;
CLR: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
signal CLR: std_logic;
signal CLK: std_logic := '0';
signal Q: std_logic_vector(3 downto 0);
EECE 320 L30: Finite State Machine Examples 8
Chehab, AUB, 2003
Modulo-10 Counter Using T FFs - VHDL
begin
U0: count10 port map (CLK, CLR, Q);
CLK <= not CLK after 10 ns;
CLR <= '1', '0' after 25 ns;
end count10_tb;
CLR
CLK
Q
ns
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U
0
1
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0
1
EECE 320 L30: Finite State Machine Examples 9
Chehab, AUB, 2003
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