EECE 320 Lecture 7, Fall 2011

EECE 320 L7: Combinational Logic design Principles 1 Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 7: Combinational Logic Design Principles Ali Chehab EECE 320 L7: Combinational Logic design Principles 2 Chehab, AUB, 2003 Minimizing Sum-of-Product  Given 2 PI’s P and Q in a reduced map, we say that P eclipses Q (P…Q) if P covers at least all 1’s that are covered by Q  If P costs no more than Q, we can disregard Q. EECE 320 L7: Combinational Logic design Principles 3 Chehab, AUB, 2003 Minimizing Sum-of-Product  Sometimes, there are no essential prime implicants, and we may have to resort to trial and error. EECE 320 L7: Combinational Logic design Principles 4 Chehab, AUB, 2003 Minimizing Product of Sums  Method 1  We try to cover all the zeros in the K-map  Each zero correspond to maxterm in the canonical product  Method 2  We complement F by interchanging 1’s and 0’s  We minimize F’ as a SOP  We complement F’ using De Morgan’s theorems to obtain a POS  To find the lowest cost of a 2-level implementation we have to compare minimal SOP and minimal POS EECE 320 L7: Combinational Logic design Principles 5 Chehab, AUB, 2003 Minimizing Product of Sums  F = (A+C+D)(A’+B’+C)(A’+D’) F’ = A’C’D’ + AD + ABC’  F = (A+C+D) (A’+D’)(A’+B’+C) CD AB 00 01 11 10 00 01 11 10 1 0 0 1 1 1 1 1 1 0 0 1 0 0 1 0 CD AB 00 01 11 10 00 01 11 10 0 1 1 0 0 0 0 0 0 1 1 0 1 1 0 1 EECE 320 L7: Combinational Logic design Principles 6 Chehab, AUB, 2003 Don’t-Care Input Combinations  Sometimes, the specifications of the circuit indicate that it doesn’t matter what is the output for some input combinations, we call them don’t-cares.  EX: 4-bit prime detector for BCD digit  F = N3,N2,N1,N0(1,2,3,5,7) + d(10,11,12,13,14,15)  To get a minimal SOP:  We include d’s when circling 1’s to obtain largest possible sets  Do not circle sets with only d’s EECE 320 L7: Combinational Logic design Principles 7 Chehab, AUB, 2003 Multiple Output Minimization  If we treat a circuit with n outputs as n independent single-output design problem we may not always get an optimal design.  EX: F = X,Y,Z(3,6,7) and G =  X,Y,Z(0,1,3) EECE 320 L7: Combinational Logic design Principles 8 Chehab, AUB, 2003 Multiple Output Minimization  However, if we consider the common term, we can reduce the cost by 1 gate EECE 320 L7: Combinational Logic design Principles 9 Chehab, AUB, 2003 Next Lecture and Reminders  Next lecture  Reminders